Chip Planner

About the Chip Planner


The Chip Planner provides a visual display of chip resources. It can show logic placement, LogicLock regions, relative resource usage, detailed routing information, fan-ins and fan-outs, paths between registers, and high-speed transceiver channels. You can view physical timing estimates, routing congestion, and clock regions.

The Chip Planner can perform assignment changes, such as creating and deleting resource assignments, as well as post-compilation changes, such as creating, moving, and deleting logic cells and I/O atoms. You can use the Chip Planner in conjunction with the Resource Property Editor, to change connections between resources and make post-compilation changes to the properties of logic cells, I/O elements, and PLLs.

To open the Chip Planner, you can click Chip Planner on the Tools menu. The Chip Planner is available for supported device  families.


ExpandUser interface and interactivity:

ExpandPresets, Tasks, Layers, and Editing Modes:

ExpandBird's Eye View:

ExpandEmbedded Assignment Editor, LogicLock Regions Window, Design Partitions Window, Resource Property Editor, and Change Manager:





For more information about Chip Planner, refer to the Altera Training page of the Altera website.



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