Quartus

Register <name> will power up to <level>

(ID: 18010)


CAUSE: You set the Power-Up Level option for the specified node. However, the power-up level can not be honored. For example, if registers do not have asynchnorous load capability on the chosen device, a register that uses asynchronous clear cannot power up to High. Similarly, if registers do not have asynchnorous load capability on the chosen device, then a register that uses asynchronous preset cannot power up to Low. Note that Quartus II Integrated Synthesis reads default values for registered signals defined in VHDL code and converts the default values into Power-Up Level settings. The software also synthesizes variables that are assigned values in Verilog HDL initial blocks into power-up conditions.
ACTION: No action is required. To avoid receiving this message in the future, Altera recommends that you turn off the Power-Up Level option or change it from High to Low or from Low to High.