Top-level design entity "<name>" is undefined

(ID: 12007)

CAUSE: You attempted to compile the current design, but the specified top-level design entity for the design is undefined. This message can occur due to a case mismatch between the top-level design entity and the entity in the Module Declaration of a Verilog Design File (.v) or Verilog Quartus Mapping File (.vqm) for the design.
ACTION: Make sure the case of the top-level design entity you specified in the General page of the Settings dialog box matches the case of the entity in the Verilog Design File or VQM. Also, make sure that the required user library paths are specified correctly. If the project contains EDIF Input Files (.edf), make sure that you specified the EDA synthesis tool settings correctly. Otherwise, define the specified top-level design entity or specify a different top-level design entity.

See also:

Compiling a Design
Specifying EDA Tool Settings
Specifying General Settings