Cannot synthesize initialized RAM logic "<name>"

(ID: 276000)

CAUSE: In a Verilog Design File (.v) or VHDL Design File (.vhd), you specified logic that acts as RAM with a specified initial value. However, Analysis & Synthesis cannot synthesize this logic properly.
ACTION: Remove any asynchronous or synchronous clear or reset logic associated with the RAM. Remove bidirectional signals from the RAM logic. Use coding styles that allow Analysis & Synthesis to infer RAM. Refer to Chapter 7, "Recommended HDL Coding Styles," in the Quartus II Handbook, vol. 1., for examples of coding styles.

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