VHDL Synthesis Attributes and Directives

 


The Quartus II software supports the following VHDL synthesis attributes and synthesis directives, which you can use in a VHDL Design File (.vhd) to direct Analysis & Synthesis to perform or not perform certain actions when synthesizing a design:

 

Attribute

Description

altera_attribute

A VHDL synthesis attribute that specifies the value of Quartus II options and assignments for VHDL objects (entities, instances, and signals).

chip_pin

A VHDL synthesis attribute that assigns device pins to a port on a VHDL entity.

direct_enable

A VHDL synthesis attribute that guides Quartus II Integrated Synthesis as to which signals it should prefer as clock enable signals to the registers.

enum_encoding

A VHDL synthesis attribute that specifies the logic encoding for an Enumeration Type.

keep

A VHDL synthesis attribute that directs Analysis & Synthesis to not minimize or remove a particular net when optimizing combinational logic.

library

A VHDL synthesis directive that sets the destination library for the design units in a VHDL Design File.

maxfan

A VHDL synthesis attribute that directs Analysis & Synthesis to duplicate a register to ensure that the register's fan-out does not exceed the maximum value you specify.

multstyle

A VHDL synthesis attribute that specifies the implementation style for multiplication operations (*) in your HDL source.

 

noprune

A VHDL synthesis attribute that prevents the Quartus II software from removing a register that does not directly or indirectly feed a top-level output or bidir pin.

preserve

A VHDL synthesis attribute that directs Analysis & Synthesis to not minimize or remove a particular register when eliminating redundant registers or registers with constant drivers.

ramstyle

A VHDL synthesis attribute that specifies the type of TriMatrix Memory block to use when implementing an inferred RAM.

romstyle

A VHDL synthesis attribute that specifies the type of TriMatrix Memory block to use when implementing an inferred ROM.

ram_init_file

A VHDL synthesis attribute that specifies initial contents of an inferred memory block.

read_comments_as_HDL

A VHDL synthesis directive that directs Analysis & Synthesis to perform logic synthesis on portions of the design code that are in comments.

syn_encoding

A VHDL synthesis attribute that specifies encodings for the states modeled by an enumeration type.

translate_off
translate_on

VHDL synthesis directives that direct Analysis & Synthesis to ignore portions of the design code that are specific to simulation and not relevant to logic synthesis.

useioff

A VHDL synthesis attribute that directs Analysis & Synthesis to implement input, output, and output enable registers in I/O cells that have fast, direct connections to an I/O pin, when possible.

vhdl_input_version

A VHDL synthesis directive that specifies the VHDL input version for the design units.

 

To use an synthesis attribute in a VHDL Design File, you must first declare the synthesis attribute in an Attribute Declaration. You can then use the synthesis attribute by associating the synthesis attribute with registers in Attribute Specifications. For example, the following Attribute Declaration declares the maxfan synthesis attribute, and the following Attribute Specification associates the maxfan synthesis attribute with the clkgen register and specifies a value of 200 for the synthesis attribute:

attribute maxfan : integer ;
attribute maxfan of clk_gen : integer is 200;

To use a synthesis directive in a VHDL Design File, you specify the synthesis directive in a comment in the file. The comment can use the following format:

-- <comment>

In the comment, precede the synthesis directive with the synthesis keyword. You can also precede the synthesis directive with one of the following keywords:

For example, you can use the following comment to use the translate_off synthesis directive in a VHDL Design File:

-- synthesis translate_off 

Synthesis attributes and directives are also known as "pragmas". Synthesis directives are also known as "logic synthesis directives."

 

 

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