The Quartus II software provides a variety of primitive functions for circuit design. AHDL, Verilog HDL, and VHDL logical operators, ports, and some statements, as well as Verilog HDL gate primitives, replace primitives in AHDL, Verilog HDL, and VHDL files. As a result, AHDL, Verilog HDL, and VHDL primitives are a subset of those available for Block Design Files (.bdf), as shown below.


ExpandBuffer Primitives:

ExpandLogic Primitives:

ExpandOther Primitives:

ExpandPin Primitives/Ports:

ExpandStorage Primitives:

ExpandPrimitive/Port Interconnections:

ExpandUnused Inputs to Primitives, Megafunctions and Macrofunctions:




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