Timing Analyzer

About Design Entry


You can use the Quartus II Block Editor, Text Editor, MegaWizard Plug-In Manager, and EDA design entry tools to create design files in a project. You create schematic or block designs with the Block Editor, or  AHDL, VHDL, or Verilog HDL designs with the Quartus II Text Editor. The MegaWizard Plug-In Manager helps you create design files with customized megafunctions.

Qsys is a powerful system integration tool which is included as part of the Quartus II software. The Qsys system-integration tool saves significant time and effort in the FPGA design process by automatically generating interconnect logic to connect intellectual property (IP) functions and subsystems. Qsys is the next-generation SOPC Builder tool powered by a new FPGA-optimized network-on-chip technology delivering higher performance, more scalable systems, and improved design reuse compared to SOPC Builder.

The Quartus II software supports EDIF Input Files (.edf) or Verilog Quartus Mapping Files (.vqm) generated by EDA design entry and synthesis tools. The following sections contain more information about design entry methods.


ExpandDesign Entry Flow:

ExpandUsing the Block Editor:

ExpandUsing the Text Editor:

ExpandUsing the MegaWizard Plug-In Manager:

ExpandCreating a System with Qsys:


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