About Synthesis


You can use the Analysis & Synthesis module of the Compiler to analyze and synthesize design files and create the project database. Analysis & Synthesis performs logic synthesis to minimize the logic usage of the design, and performs technology mapping to implement the design logic using device resources such as logic elements. Finally, Analysis & Synthesis generates a single project database integrating all the design files in a design.

Analysis & Synthesis uses Quartus II Integrated Synthesis to synthesize your Verilog Design Files (.v) or VHDL Design Files (.vhd). You may use other EDA synthesis tools to synthesize your Verilog Design Files or VHDL Design Files, and then generate an EDIF netlist file (.edf) or a Verilog Quartus Mapping File (.vqm) that you can use with the Quartus II software.

You can start a full compilation, which includes the Analysis & Synthesis module, or you can start Analysis & Synthesis with the Start Analysis & Synthesis command for a design. The Quartus II software also allows you to perform an Analysis & Elaboration to check design files for syntax and semantic errors, or use the Analyze Current File command to check a single design file for syntax errors. These commands do not perform logic synthesis or technology mapping on the design logic.


ExpandSynthesis Flow:

ExpandHow Analysis & Synthesis Works:

ExpandSynthesis Settings:

ExpandIntegrated Synthesis:

ExpandTiming-Driven Synthesis:

ExpandPhysical Synthesis:


Scripting Information

Executable: quartus_map


You can run Analysis & Synthesis separately at the command line prompt or in a script with the quartus_map executable. The quartus_map executable creates a new project if one does not already exist, and creates a separate text-based report file that can be viewed with any text editor.


More information is available on the Compiler on the Altera website.



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