About Simulating Designs

 


Simulation verifies design behavior before programming a device. The Quartus II software supports and integrates industry standard RTL and gate-level EDA simulators. RTL simulation is cycle-accurate verification of your HDL source code and the simulation models provided by Altera and other IP providers. Gate-level simulation verifies the functionality of a design after synthesis (post-synthesis functional netlist), after synthesis and fitting  (post-fit functional netlist), or after timing analysis (post-fit timing netlist).

Simulating Altera designs involves setting up the simulator work environment, compiling simulation model libraries, and running your simulator. The Quartus II software supports automated and custom simulation flows. You can use the Quartus II NativeLink feature to automatically generate simulation files and scripts for compiling simulation source files (including design files, Altera simulation models, IP, and testbench files). NativeLink then launches your simulator automatically from within the Quartus II software. Use a custom flow if you require greater control.

 

ExpandSimulation Flow Diagram:

 

More information is available about simulation on the Altera website.

 

 

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