The Intel® Stratix® 10 Tools Support page provides links to interactive tools and other support resources to speed your design activity.  Tools and resource aids are grouped by category.  Technical documents are located on the Documentation tab (above) and educational and training content is located on the Learn tab (above).   Use the buttons below or scroll down to view Tool category contents.

This page supports Tools for all Intel® Stratix® 10 GX / TX / SX , MX and DX Devices.

 

 

Models

Resource Description
BSDL Browse boundary-scan description language (BSDL) files by specific available devices and choose the appropriate device package. 
BSDL Support Intel provides boundary-scan description language (BSDL) files for IEEE Standard 1149.1, IEEE Standard 1149.6 and IEEE Standard 1532 specifications. If you want to perform BST after configuration, you can select the appropriate generation tools and guidelines for the post-configuration BSDL generation in Table 1 on this linked page
IBIS IBIS models for Intel® devices support a wide variety of I/O features and cover minimum, typical, and maximum process, voltage, and temperature conditions.  Select models of interest from table 2 on the linked page.
HSPICE SPICE kits enable you to perform system-level simulations for various configurations that make use of Intel Stratix 10 devices.   LVDS and 3V IO models are available. Select models of interest from table 2a on the linked page.

Board

Resource Description
PIN OUT Information Intel Stratix 10 Pin Out tables by device density - available in PDF, XLS or TXT formats.  External memory Interface (EMIF) and Hard processor System (HPS) pin information tables are also available. 

Pin Connection Guidelines (HTML) /

Pin Connection Guidelines (PDF)

Intel Stratix Device Family Pin Connection Guidelines - available in HTML or PDF format.
Package Mechanical Drawings Intel Stratix 10 package dimensions and mechanical drawings are downloaded as PDF documents.  Select by Device or Part Number.
Schematic Review Worksheet (doc download) Intel® Stratix® 10 schematic review worksheet is intended to help you review your schematic and adhere to Intel's guidelines. The worksheet is based on the respective device Pin Connection Guidelines and other referenced Intel FPGA documentation applicable to board-level pin connections that needs to be considered when you finalize your schematic.
Manufacturing Recommendations Manufacturing with Intel Stratix 10 Field Programmable Gate Arrays - information on Component Attributes and drawings, Assembly and rework process, stencil design and X-Ray exposure time recommendations.  PDF format.

Power

Resource Description
Power Distribution Network The easy-to-use power distribution network (PDN) design tool is a graphical tool used with all Intel® FPGAs to optimize the board-level PDN.  Page provides links to the PDN Tools and documentation.

Intel Stratix  10 Device Early Power Estimator

 

User Guide for Intel Stratix 10 EPE

 

Early Power Estimators and Power Analyzer Tool (EPE) for Intel Stratix 10 Devices - Download the Tool and EPE user Guide - View the EPE Overview page.
Power Solution for Intel® Stratix® 10 FPGAs Validated Power Solutions Designed for Intel® Stratix® 10 FPGAs and SoC FPGAs.

Development Kits (Dev Kits) and Design Examples

Resource Description
Stratix 10 Design Examples Visit the Intel FPGA Design Store to view available Intel Stratix 10 Design Examples.
Stratix 10 GX FPGA Dev Kit The Intel Stratix 10 GX FPGA Development Kit delivers a complete design environment that includes all hardware and software you need to start taking advantage of the performance and capabilities available in Stratix 10 GX FPGAs for your design needs.
Stratix 10 GX Signal Integrity Dev Kit The Intel Stratix 10 GX Signal Integrity Development Kit delivers a complete design environment that includes all hardware and software you need to start taking advantage of the performance and capabilities available in Stratix 10 GX FPGAs for your design needs.
Intel® Stratix® 10 TX Signal Integrity Dev Kit The Intel Stratix 10 TX Signal Integrity (SI) Development Kit offers a complete design environment that includes both hardware and software for developing Intel Stratix 10 TX FPGA designs. 
Stratix 10 SX SoC Dev Kit The Intel Stratix 10 SoC Development Kit offers a quick and simple approach for developing custom ARM* processor-based SoC designs. The Stratix 10 SoCs offer full software compatibility with previous generation SoCs, a broad ecosystem of ARM software and tools, and the enhanced FPGA and digital signal processing (DSP) hardware design flow.
Stratix 10 MX FPGA Dev Kit The Intel Stratix 10 MX FPGA Development Kit delivers a complete design environment that includes all hardware and software you need to start taking advantage of the performance and capabilities available in Stratix 10 MX FPGAs for your design needs
Stratix 10 DX FPGA Dev Kit The Intel Stratix 10 DX FPGA Development Kit delivers a complete design environment that includes all the hardware and software within a PCIe form factor. The board enables users to develop and test their PCIe designs with Stratix 10 DX FPGAs, which feature new transceiver technology for PCIe Gen4 support. 
All Intel Stratix Dev Kits See all Stratix Development Kits from Intel and Partners. On this page, select the Stratix 10 family of interest in the "Devices" pick list box on the page.

HPS (SoC)

Resource Description

HPS Address Map and Definitions (HTML)

HPS Address Map and Definitions (ZIP Download)

Intel Stratix 10 SoC HPS Address Map and Register Definitions.  Available in HTML format or as a downloadable ZIP file.
Embedded Systems - Support Center

Expand your understanding of software development for Intel’s SoC FPGAs and Nios® II soft intellectual property (IP) processors. 

Links for: Linux*, SoC Bare-Metal, Nios II Bare-Metal Developers and also SoC Bootloader.

XCVR - Transceiver

Resource Description
Transceiver Toolkit  Transceiver Toolkit uses System Console technology to help FPGA and board designers validate transceiver link signal integrity real time in a system and improve board bring-up time. 
Transceiver PHY IP - Support Center
Information on how to select, design, and implement transceiver links. Also guidelines on how to bring up your system and debug the transceiver links.
Ethernet IP - Support Center
Information on how to select, design, and implement Ethernet links. Also guidelines on how to bring up your system and debug the Ethernet links.
PCI Express IP - Support Center
Information on how to select, design, and implement PCIe links. Also guidelines on how to bring up your system and debug the PCIe links.

General

Resource Description

S10 GX Overview Table

S10 SX Overview Table

S10 TX Overview Table

S10 MX Overview Table

S10 DX Overview Table

Download family specific product overview tables in PDF format.  Displays Resources and Features versus device.
EMIF Spec Estimator - Tool The External Memory Interface Spec Estimator is a parametric tool that allows you to find and compare the performance of the supported external memory interfaces in Intel® FPGAs.
External Memory Interface IP - Support Center Information on how to plan, design, implement, and verify your external memory interfaces.
Device Configuration - Support Center Information on how to select, design, and implement configuration schemes and features. Also guidelines on how to bring up your system and debug the configuration links.
All Support Centers  Step-by-Step Guidance for System Architect Developers, FPGA developers, Embedded Software developers, and Board Developers.  Additional Technology Support Centers.

Additional support resources: