XS4 10-Gigabit Ethernet & HiGig SPI-4.2 Bridge Reference Design

The use of this design is governed by, and subject to, the terms and conditions of the Intel Design Example License Agreement.


The XS4 (XAUI SPI-4.2) Bridge from MorethanIP provides a cost effective and integrated solution to bridge an SPI4.2 interface to a XAUI interface. The XS4 Bridge provides a generic solution to meet multiple design requirements such as device bridging (e.g., NPU to Ethernet Switch), serial backplane applications, and Packet over SONET/SDH (POS) or Ethernet over SONET/SDH (EOS) applications. The MAC also implements a HiGig mode, which can used to interface with broadcom switches. Features include:

  • MAC layer and reconciliation sub-layer implementation compliant with IEEE 802.3ae specification with HiGig Mode to interface broadcom switch devices
  • Bridge can be delivered with a XGMII or a XAUI interface
  • Large embedded FIFO buffers with automatic flow control with pause frame generation from programmable congestion thresholds
  • SPI-4.2 interface compliant with PMC-Sierra PMC-1991635 specification document with 16-bit LVDS DDR operating at rates of 800 Mbps per pin
  • Complete set of error event counters providing application management and application monitoring accessible via host processor interface

Demonstrated Intel Technology

Block Diagram:

Figure 1. XS4 Bridge With Block Diagram

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Contact Information

MorethanIP Gmbh
Münchner Strasse 199
D-85757 Karlsfeld
Tel: +49 81313339390
Fax: +49 81313339391
Email: info@morethanip.com
URL: www.morethanip.com

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