PCI to Local Bridge Reference Design

The use of this design is governed by, and subject to, the terms and conditions of the Intel Design Example License Agreement.

Overview

Most PCI chips and cores only implement the minimum PCI bus interface signaling. This leaves the burden of connectivity, performance, and system compatibility on the designer. This reference design illustrates how you can enhance the pci_t32 MegaCore® function to provide a set of advanced features to provide the best possible performance and flexibility to simplify the design. The design implements a 32-bit 66-MHz local bus.

Features

  • PCI local bus specification r2.2 vital product data configuration support
  • Flexible local bus provides 32-bit multiplexed or non-multiplexed protocol for 8-, 16-, or 32-bit peripheral and memory devices
  • Nine programmable general-purpose I/O pins
  • Five programmable local address spaces
  • Four programmable chip selects
  • Programmable local bus wait states
  • Two programmable local-to-PCI interrupts
  • Endian byte swapping
  • Local address remap

Demonstrated Intel Technology

Figure 1. PCI to Local Bridge Reference Design Block Diagram

Contact Information

Dexcel Electronics Designs (P) Ltd,
Unit 505, Carlton Towers,
#1, Airport Road
Bangalore 560008, India.

Tel: +91 80 25216221, 25216222
Fax: +91-80-2521 6791
info@dexceldesigns.com
www.dexceldesigns.com

Reference Designs Disclaimer

These reference design illustrations may be used within Intel Corporation devices only and remain the copyrighted property of Intel. They are being provided on an "as-is" basis and as an accommodation, and therefore all warranties, representations, or guarantees of any kind (whether express, implied or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Intel expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Intel.