WCDMA DUC and DDC Reference Designs

from Intel

These reference designs are included in DSP Builder for Intel FPGAs version 8.0 or later. The use of these designs are governed by, and subject to, the terms and conditions of the Hardware Reference Design License Agreement.


The WCDMA digital upconverter (DUC) and digital downconverter (DDC) reference designs demonstrate how system architects and hardware designers can accelerate the design of DUC and DDC functions for WCDMA basestations using Intel® devices, tools, and intellectual property (IP). The designs are based on the DSP Builder for Intel FPGAs (Advanced Blockset) technology and illustrate how the tool significantly increases productivity while delivering high-performance, cost-effective digital IF designs.


  • DSP Builder for Intel FPGAs (Avanced blockset)-based design methodology significantly reduces development time
  • Multichannel filter design techniques to achieve cost-effective solutions
  • Support for multiple transmit and receive antenna configurations
  • Easily modifiable to support scalable channel bandwidths and macro and picocell base transceiver
    station (BTS)

Demonstrated Intel Technology

Block Diagram

Figure 1. WCDMA DUC (4 Carrier, 1 Sector, Diversity)


  1. FIR = Finite impulse response
  2. NCO = Numerically controlled oscillator
  3. CIC = Cascaded integrator-comb

Related Links

Reference Designs Disclaimer

These reference design illustrations may be used within Intel  Corporation devices only and remain the copyrighted property of Intel. They are being provided on an "as-is" basis and as an accommodation, and therefore all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Intel expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Intel.