These reference designs are included in DSP Builder for Intel FPGAs version 8.0 or later. The use of these designs are governed by, and subject to, the terms and conditions of the Hardware Reference Design License Agreement.
The WCDMA digital upconverter (DUC) and digital downconverter (DDC) reference designs demonstrate how system architects and hardware designers can accelerate the design of DUC and DDC functions for WCDMA basestations using Intel® devices, tools, and intellectual property (IP). The designs are based on the DSP Builder for Intel FPGAs (Advanced Blockset) technology and illustrate how the tool significantly increases productivity while delivering high-performance, cost-effective digital IF designs.
- DSP Builder for Intel FPGAs (Avanced blockset)-based design methodology significantly reduces development time
- Multichannel filter design techniques to achieve cost-effective solutions
- Support for multiple transmit and receive antenna configurations
- Easily modifiable to support scalable channel bandwidths and macro and picocell base transceiver