The use of this design is governed by, and subject to, the terms and conditions of the Intel Design Example License Agreement
FPGAs are very well suited for bit rate processing in an LTE (or WiMAX) channel card application. Support for variable bandwidth and multiple sectors require the solution to be scalable. Altera’s LTE Turbo Decoder reference design is based on the 3GPP LTE specification and is designed for scalability. The decoder also supports early termination. The solution is based on extensive systems analysis that provides the required throughput with a resource-efficient architecture and superior performance including bit-error rate (BER) and latency. This reference design was tested and validated against an extensive verification methodology. The solution also offers a choice of run-time and compile-time parameters.
The 3GPP LTE Turbo Decoder reference design is complemented with the 3GPP LTE Turbo Encoder reference design. The LTE Turbo Encoder performs turbo encoding with trellis termination support.
Other deliverables that might also be of interest include:
- C/MATLAB bit-accurate models for performance simulation or register transfer level (RTL) test vector generation
- Generation of VHDL or Verilog HDL test benches using the MegaWizard® Plug-In Manager
Please contact your local Intel sales representative for a copy of this reference design.