The use of this design is governed by, and subject to, the terms and conditions of the Intel Design Example License Agreement.
In the telecommunications industry, it is common practice to require both digital signal processing (DSP) capabilities and network processing unit (NPU) capabilities within the same system. This occurs when data must be extracted from modulated data streams, which often consist of protocols that require further processing. To properly communicate, the DSP processor and the NPU processor require two specific “paths” between each other. One is the data path extracted from the modulated data streams. With the Intel IXP2350/IXP2325 series of NPU processors and Analog Devices Incorporated's (ADI's) TigerSHARC combination, this is provided through a link-port, System Packet Interface Level 3 (SPI-3) path. The other path is the control plane, which provides a means to communicate control information between the IXP2350/IXP2325 and TigerSHARC through the Cluster Bus–Expansion Bus path. This reference design is a solution to the control plane bridge required when using ADI's TigerSHARC DSP processor and Intel IXP2350/IXP2325 series of NPU processors.