from Quasar Systems, Inc.
The use of this design is governed by, and subject to, the terms and conditions of the Hardware Reference Design License Agreement.
Overview
In the telecommunications industry, it is common practice to require both digital signal processing (DSP) capabilities and network processing unit (NPU) capabilities within the same system. This occurs when data must be extracted from modulated data streams, which often consist of protocols that require further processing. To properly communicate, the DSP processor and the NPU processor require two specific “paths” between each other. One is the data path extracted from the modulated data streams. With Intel's IXP2350/IXP2325 series of NPU processors and Analog Devices Incorporated's (ADI's) TigerSHARC combination, this is provided through a link-port, System Packet Interface Level 3 (SPI-3) path. The other path is the control plane, which provides a means to communicate control information between the IXP2350/IXP2325 and TigerSHARC through the Cluster Bus–Expansion Bus path. This reference design is a solution to the control plane bridge required when using ADI's TigerSHARC DSP processor and Intel's IXP2350/IXP2325 series of NPU processors. A block diagram of this reference design can be seen in Figure 1.
Figure 1. IXP2350/IXP2325-TigerSHARC Block Diagram
Requirements
The Control Plane Bridge Reference Design requires three basic functions:
- Boot-Up Mechanism for the TigerSHARC DSP Processor—The TigerSHARC DSP processor requires initialization, or boot up, after a reset. The DSP processor is capable of three boot options for beginning operation: EPROM boot, host boot, and link-port boot. The reference design utilizes the EPROM boot method. The IXP2350/IXP2325 NPU provides this boot-load code via a 1-Kbyte boot FIFO buffer (see Figure 2).
- Control Plane Communication Path Between the DSP Processor & NPU—The DSP processor and the NPU require a communications path to pass the appropriate control plane information. This consists of two FPGA internal SRAMs and an interrupt mechanism. The two SRAMs (see Figure 2, “SRAM N2D” and “SRAM D2N”) facilitate message passing between the DSP processor and the NPU. The interrupt mechanism provides a means to interrupt either the NPU processor or the DSP processor when data has been placed into the appropriate SRAM.
- Control & Status Mechanism—The control plane bridge requires the following registers:
- Control registers to control the DSP processor reset and DSP processor boot process
- Status registers to enable the NPU to obtain the operational status of the DSP processor and the DSP processor to obtain operational status of the NPU
- Interrupt status registers to obtain the interrupt status for both the DSP processor and NPU
- Interrupt control registers to enable both the NPU and DSP processor to mask and clear their respective interrupts
Block Diagram
Figure 2 shows a high-level block diagram of the reference design. The reference design consists of the following elements:
- SRAM N2D (2 Kbytes) utilized for the NPU to DSP processor direction only, and therefore can be read or written by the NPU and is read-only by the DSP processor
- SRAM D2N (2 Kbytes) utilized for the DSP processor to NPU direction only, and therefore can be read or written by the DSP processor and is read-only by the NPU
- Registers
- TigerSHARC boot FIFO buffer (1 Kbyte) for EPROM boot
Figure 2. Reference Design Block Diagram
Intel Demonstrated Technology
Contact Information
Scott Walker
Vice President, Engineering
Quasar Systems Inc.
22648 Glenn Drive, Suite 104
Sterling, VA 20164
Phone: 703-467-8075
Cell: 571-215-9521
Email: Scott.Walker@QuasarSystemsInc.com
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