WiMAX DUC and DDC Reference Designs

These reference designs are included in DSP Builder version 8.0 or later (you can download the Arria® II GX FPGA version by clicking Download Reference Design). The use of these designs are governed by, and subject to, the terms and conditions of the Intel Design Example License Agreement.


The WiMAX digital upconverter (DUC) and digital downconverter (DDC) reference designs demonstrate how system architects and hardware designers can accelerate the design of DUC and DDC functions for WiMAX basestations using Intel® devices, tools, and intellectual property (IP). The designs are based on the DSP Builder advanced blockset technology and illustrate how the tool significantly increases productivity while delivering high-performance, cost-effective digital IF designs.


  • DSP Builder advanced blockset-based design methodology significantly reduces development time
  • Multi-channel filter design techniques to achieve cost-effective solutions
  • Support for multiple transmit and receive antenna configurations
  • Easily modifiable to support scalable channel bandwidths
  • Compliant to the draft WiMAX standard (IEEE 802.16)

Demonstrated Intel Technology

Figure 1. Single Channel IQ Time Division Multiplexed DUC


  1. FIR = Finite impulse response.
Figure 2. Single Channel IQ Time Division Multiplexed DDC


  1. NCO = Numerically controlled oscillator.

Reference Designs Disclaimer

These reference design illustrations may be used within Intel Corporation devices only and remain the copyrighted property of Intel. They are being provided on an "as-is" basis and as an accommodation, and therefore all warranties, representations, or guarantees of any kind (whether express, implied or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Intel expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Intel.