Please contact your local Intel sales representative for a copy of this reference design. The use of this design is governed by, and subject to, the terms and conditions of the Hardware Reference Design License Agreement.
You can use the discrete Fourier transform (DFT)/inverse DFT (IDFT) reference design to accelerate the implementation 3rd Generation Partnership Project (3GPP) long term evolution (LTE)-based wireless networks. DFT/IDFT is a key component of the LTE PHY layer, with the DFT functionality being required on the terminal side and IDFT on the basestation side. This reference design demonstrates the suitability of Stratix® and Arria® series FPGAs for implementing high-performance, low-latency DFT/IDFT functionality.
Intel supplies the reference design as clear-text VHDL, including a fixed-point MATLAB simulation model.
- Supports all of the 34 transform sizes specified in the 3GPP LTE standard
- Supports run-time configuration on a block-by-block basis between the transform sizes
- User-defined inputs for specifying transform mode (DFT or IDFT) and internal bit widths
- Supports complex input and output sequences
- Highly optimized design targeting efficient use of Stratix II and Stratix III FPGA resources
Demonstrated Intel Technology
Figure 1 shows the DFT/IDFT reference design blocks.