Single-Port Triple-Speed Ethernet On-Board PHY Chip Reference Design

The use of this design is governed by, and subject to, the terms and conditions of the Intel® Design Example License Agreement.


Single-Port Triple-Speed Ethernet On-Board PHY Chip datapath reference design provides a simple and quick way to implement your own Ethernet-based design in an Intel® FPGA. The reference design also observes live network traffic flowing through a loop-back Ethernet cable or a Gbps Ethernet switch. This design also helps you to verify your Ethernet-based system operation with an Altera University of New Hampshire (UNH) verified Triple Speed Ethernet function and a standard off-the-shelf Ethernet PHY device. You can leverage this design to build your own Ethernet system with low risk and minimal effort.

The reference design is built with Intel Qsys using one instances of the Triple-Speed Ethernet MegaCore® function in a Stratix® IV GX or Arria® II GX FPGA with on-board Marvell 88E1111 PHY chips. This reference design demonstrates the operation of the Triple-Speed Ethernet MegaCore function up to the maximum wire-speed performance in loop-back hardware configuration.


  • Require minimal hardware for a complete test.
  • Implement one instance of the Triple-Speed Ethernet intellectual property (IP) core and support 10/100/1000- megabits per second (Mbps) Ethernet operations in the following modes:
    • RGMII mode on the Arria II GX design
    • SGMII mode with auto-negotiation on the Stratix IV GX design
  • Support programmable test parameters such as number of packets, packet length, source and destination media access control (MAC) addresses, and payload-data type.
  • Support testing with sequential random bursts, which enables the configuration of each burst for the number of packets, payload-data type, and payload size. A pseudo-random binary sequence (PRBS) generator generates the payload data type in fixed incremental values or in a random sequence.
  • Demonstrate transmission and reception of Ethernet packets through internal loopback path at the maximum theoretical data rates without errors.
  • Include support for gathering throughput statistics.
  • Supports System Console user interface. This user interface, which is based on Tcl, allows you to dynamically configure, debug, and test the reference designs.

Demonstrated Intel Technology

  • Stratix IV GX FPGAs
  • Arria II GX FPGAs
  • Triple-Speed Ethernet MegaCore function
  • Platform Designer
  • Avalon® system interconnect fabric
Figure 1. Single-Port Triple-Speed Ethernet On-Board PHY Chip Reference Design

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