Drive-on-a-Chip Multi-axis Motor Control Reference Design

The use of this design is governed by, and subject to, the terms and conditions of the Intel Hardware Reference Design License Agreement.

Overview

The Intel drive-on-a-chip motor control reference design is an integrated drive system on a single Cyclone® V SoC or Intel® MAX® 10. The design implements single- and multiaxis field-oriented control (FOC) supporting concurrent control of up to four permanent magnet synchronous motors. The reference design showcases a software-centric design flow for motor control on FPGAs. It targets either the dual ARM* Cortex*-A9 hard processor system or the Nios® II soft-core processor as the drive system host integrated with DSP co-processors and key motor control interface IP in the FPGA. This demonstrates the cost-effective scalability of integrated drive-on-a-chip designs on Intel's Cyclone families and is an excellent starting point for your own drive system design.

Features

  • Complete software system running on either the dual ARM Cortex-A9 hard processor system or Nios II processor, performing high-level control and configuration (in addition to closing of motor position and speed loops)
  • Software-only and FPGA-accelerated FOC implementations that integrate position and speed loops in software with an ultra-low latency, high-performance current control loop in the FPGA as a DSP coprocessor
  • Optimized and software-configurable FOC IP subsystem, customizable in DSP Builder with support for both fixed- and floating-point precision implementations
  • Integrates key motor control functions such as space vector pulse-width modulation (PWM), Sigma-Delta ADC interface and filter logic, and position feedback encoder interfaces in the FPGA, all under control of software

Demonstrated Intel Technology

Hardware Requirements

  • Intel Multiaxis Motor Control Board with either Intel Cyclone V Development Kit or INK Development Kit from Terasic

Software Requirements

Intel Quartus® software version 17.0 or later with the following features:

Block Diagram

The reference design, as shown in Figure 1, implements a software-configurable field-oriented-control (FOC) algorithm for concurrent control of up to two permanent magnet synchronous motors integrated with key motor control interface intellectual property (IP).

Figure 1. Drive-on-a-Chip Reference Design Block Diagram

Reference Designs Disclaimer

These reference design illustrations remain the copyrighted property of Intel or its licensors and may be used within Intel devices only. They are being provided on an "as-is" basis and as an accommodation, and therefore all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Intel expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Intel.