The ADI parallel port SDRAM controller reference design connects SDRAM to the parallel port of an Analog Devices Incorporated (ADI) ADSP-2126x Sharc digital signal processor and is implemented in Intel® FPGAs and CPLDs. Altera supplies the reference design as Verilog HDL source code. The reference design includes a testbench that allows you to test the Verilog HDL source code. The purpose of this reference design is to demonstrate that Intel devices provide a low cost SDRAM interface for ADI Sharc digital signal processors.
- Runs on the ADDS-21261 Cyclone® FPGA evaluation kit
- Requires 250 to 300 logic elements, no RAM, and 49 pins
- SDRAM controller supports the 8-bit mode of the ADSP-2126x parallel port
- Digital signal processing (DSP) core clock CCLK has a maximum frequency of 200 MHz
- Memory controller supports operation at 66 Mbps