Cyclone® III Active Parallel Remote System Upgrade Reference Design

The use of this design is governed by, and subject to, the terms and conditions of the Intel Design Example License Agreement.


System designers face difficult challenges today such as shortened design cycles, evolving standards and system deployments in remote locations. Cyclone® III FPGAs help overcome these challenges with its inherent re-programmability and dedicated circuitry to perform remote system upgrades (RSUs). Cyclone III FPGAs support the RSU feature in active parallel (AP) and active serial (AS) mode.

This reference design shows you how to use the Cyclone III RSU feature in AP mode. Cyclone III FPGAs are able to receive new configuration data from a remote source, update the flash memory content, and reconfigure itself with the new configuration data. In this reference design example, user logic is instantiated in the design to interface with the altremote_update megafunction, directing the RSU circuitry to initiate the reconfiguration cycle. The user logic is written specifically to complement the altremote_update megafunction and educates you on altremote_update megafunction usage. This document is targeted for the Cyclone III Starter Kit Board and is useful to get started with the RSU feature using the Cyclone III FPGAs.

Reference Designs Disclaimer

These reference design illustrations may be used within Intel® Corporation devices only and remain the copyrighted property of Intel. They are being provided on an "as-is" basis and as an accommodation, and therefore all warranties, representations, or guarantees of any kind (whether express, implied or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Intel expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Intel.