Video Over IP Reference Design

The use of this design is governed by, and subject to, the terms and conditions of the Intel Design Example License Agreement.


The video over IP reference design demonstrates transmission of MPEG-2 transport stream (TS) data over internet protocol (IP)-based networks. The reference design bridges one or more compressed video streams and IP packets carried over 100 megabits per second (Mbps) or 1-Gbps Ethernet.

The reference design accepts TS data and encapsulates it for transmission over Ethernet when functioning as a TS-to-Ethernet bridge (see Figure 1). Using the Ethernet-to-TS Bridge function, the design can also receive frames from Ethernet and generate TS data.

Figure 1. Video over IP Reference Design Block Diagram

The TS interface supports 188- and 204-byte packets as standardized for digital video broadcasting (DVB) MPEG-2 transport. The reference design supports both multi-program TS (MPTS) and single-program TS (SPTS) data. The reference design does not attempt to identify or separate individual programs from an MPTS input.

The Asynchronous Serial Interface (ASI) MegaCore® function can connect the TS interface to a DVB-ASI.

On the transmit side, encapsulation of the TS data for Ethernet uses IP and the user datagram protocol (UDP), with real-time transport protocol (RTP) encapsulation and Pro-MPEG code of practice #3(COP3) forward error correction (FEC) as an option. Dedicated hardware performs the encapsulation, which maximizes the throughput of the reference design and minimizes latency.

On the receive side, the design can accept traffic from Ethernet network and recover TS data. For RTP encapsulated data, the design includes a receive buffer to absorb network jitter and correct for packet reordering and packet duplication. COP3 FEC-based lost packet recovery is available as an option.

For multiple TS interfaces, the reference design individually maps each one to a specific UDP/IP socket (a combination of IP address and UDP port). All other encapsulation parameters can also be individually configured per TS.

The reference design includes a Nios® II processor. Software running on the processor configures the operation of the reference design and manages any Ethernet traffic.


  • TS-to-Ethernet bridge
  • Ethernet-to-TS bridge
  • Supports 256 individual A/V streams
  • Video transport at Ethernet line rates (100/1000 Mbps)
  • Dedicated hardware for line speed UDP/IP encapsulation and packet classification
  • Optional real-time protocol (RTP) encapsulation with Pro-MPEG #3 (COP3) forward error correction (FEC)
  • Software support for management protocols on the Nios II processor
  • Parallel TS interface and ASI connectivity

These reference design illustrations may be used within Intel Corporation devices only and remain the copyrighted property of Intel. They are being provided on an "as-is" basis and as an accommodation, and therefore all warranties, representations, or guarantees of any kind (whether express, implied or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Intel expressly does not recommend, suggest, or requirethat these examples be used in combination with any other product not provided by Intel.