from Northwest Logic, Inc.
Block Diagram
Block DiagramFigure 1 shows the block diagram for the megafunction.
Figure 1. Block Diagram for the Megafunction
Figure 1 shows the block diagram for the megafunction.
Figure 1. Block Diagram for the Megafunction
Northwest Logic's RLDRAM II Controller intellectual property (IP) core is designed for use in applications requiring high memory throughput, high clock rates, and full programmability.
The core has been optimized to take advantage of the fast random cycle and fast access times available with RLDRAM II. The core supports both common and separate data buses and multiplexed and non-multiplexed addressing.
The core accepts commands using a simple local interface and translates them to the command sequences required by RLDRAM II devices. The core also performs all initialization and refresh functions.
The core is provided with run-time programmable inputs for all memory timing parameters and configuration settings. This ensures compatibility with all RLDRAM II configurations.
Add-on cores such as a multiport front-end and reorder core can be optionally delivered with the core. The core is deiivered fully integrated and verified with the target DDR PHY. Northwest Logic supports a broad range of third party and its own soft DDR PHY. Contact Northwest Logic for more information.
Northwest Logic also provides IP core customization services. Contact Northwest Logic for a quote.
Contact Northwest Logic.
For additional information, contact Northwest Logic, Inc. at:
Northwest Logic, Inc.
1100 NW Compton Drive, Ste. 100
Beaverton, OR 97006
Tel: (503) 533-5800 x309
Fax: (503) 533-5900
Email: info@nwlogic.com
Website: www.nwlogic.com