Avalon Multi-Port SDRAM Memory Controller

from Microtronix Inc.

Features

  • Supports multiple Avalon® system interconnect ports
  • FIFO interface enables independent clock domains for memory and local bus ports
  • Up to 8 Avalon-MM port interfaces
  • Complete DDR/DDR2 controller solution, including PHY
  • Source-synchronous, DSQ-based data capture supports memory data rates to 220 and 333 MHz in Cyclone® II and Cyclone III and Stratix® II and Stratix III FPGAs
  • Memory controller supports burst memory RD/WR access cycles and handles all memory tasks, including initialization and refresh cycles
  • Each Avalon system interconnect port has user-configurable FIFO to boost performance of streaming data applications
  • Configurable FIFO depth and release threshold parameters minimize system wait-states
  • Optimized for streaming data applications, the Avalon ports support 3 modes of operation: random slave, streaming slave, and pipelined burst
  • Memory data widths up to 128 bits. Local bus width from 16 to 256 bits
  • FIFO—memory data transfers are handled as burst memory accesses
  • Round-robin port arbitration (standard)
  • Configuration GUI streamlines design process
  • Support for On-Die Termination
  • Intellectual property (IP) functional VHDL simulations model
  • Supported devices: Cyclone, Cyclone II, Cyclone III, Stratix, Stratix II, Stratix II GX, Stratix III, and Arria® GX FPGAs
  • You can customize the core to video/image applications, additional ports, or for other user requirements
  • Source code license available (VHDL)
  • OpenCore Plus evaluation
Figure 1 shows the block diagram for Microtronix Avalon Multi-Port SDRAM Memory Controller.

Description

The Microtronix Avalon Multi-Port SDRAM Memory Controller IP Core is designed for building low latency Avalon-MM-based, multi-master streaming data systems. Its advanced design features enable maximum system clock rates using low-speed FPGAs and standard memory devices. The easy-to-use memory controller simplifies memory designs by supporting 100, 133, 167, 200, 267, and 300 MHz. SDR, DDR, DDR2, and mobile DDR memory devices use a single Avalon system interconnect. A proprietary source-synchronous data synchronization design feature enables maximum system clock rates using low-speed FPGAs and standard-memory devices.

The SDRAM memory controller has up to ten Avalon ports. For example, you can use the first port for processor instruction and data words. The other ports can serve as interfaces for video and audio data or can simply be disabled. You can configure each port for:

  • Avalon random slave
  • Avalon streaming slave
  • Avalon pipelined burst

The ports use a round-robin bus arbitration system.

By using a multi-port memory controller, you can partition the Avalon system bus architecture of the system-on-a-chip (SoC) design and optimize the performance of each sub-system. Each port is supported with a data FIFO/cache which effectively doubles memory bandwidth over traditional single cache SDRAM IP cores. You can tailor FIFO/cache depth for either streaming or random access.

The core handles all memory tasks, including initialization and refresh cycles. Since the SDRAM controller is designed to operate asynchronous of the system clocks, you can clock the SDRAM devices at their peak rated frequency, maximizing performance.

The Avalon Multi-Port SDRAM Memory Controller core uses a proprietary source-synchronous clocking technology to improve the capture of SDRAM data. By making data capture independent of a phase-locked loop (PLL) system clock, timing margins are relaxed, increasing memory performance to 200 and 333 MHz in Cyclone II and Cyclone III and Stratix II and Stratix III FPGAs. This unique source-synchronous clocking technique also frees the IP core design task from the PCB design step and reduces the FPGA design compilation to a simple two-step process.

You can easily customize the core for bus data width or other arbitrations schemes, additional system ports can be supported, and source code is available for purchase.

The core is optimized for Altera® Cyclone, Arria® GX, and Stratix families of programmable logic devices and supplied as a SOPC Builder Ready component for ease of configuration.

Device Utilization Examples

Table 1 lists the typical device utilization results for the Avalon Multi-Port SDRAM Memory Controller.

Table 1. Typical Device Utilization for the Megafunction

Altera
Target Devices
Speed Grade Utilization

Performance
fMAX

Parameter Setting
LEs (1) M4K Blocks
Cyclone III-61,5502220 MHzContact Microtronix
Arria GX-61,5502267 MHzContact Microtronix
Stratix II GX-31,5502300 MHzContact Microtronix
Stratix III-21,5502333 MHzContact Microtronix

Note:

  1. The logic element (LE) count for Stratix II FPGAs is based on the number of adaptive look-up tables (ALUTs) used for the design, as reported by the Quartus® II software.

Deliverables

Avalon Multi-Port SDRAM Memory Controller IP Core Designer Package (PN: 6240-01-01)

  • Encrypted source code
  • GUI Configuration interface
  • ModelSim®/VHDL precompiled simulations library
  • Reference designs for Altera and Microtronix development kits
  • Single or multi-user licensing
  • Technical support

Contact Information

For additional information, contact Microtronix Datacom Ltd. at:

Microtronix
9-1510 Woodcock Street
London, ON, Canada N6H 5S1
Tel: +1 (519) 690-0091
Fax: +1 (519) 690-0092
Email: sales@microtronix.com
URL: www.microtronix.com