The Microtronix Avalon Multi-Port SDRAM Memory Controller IP Core is designed for building low latency Avalon-MM-based, multi-master streaming data systems. Its advanced design features enable maximum system clock rates using low-speed FPGAs and standard memory devices. The easy-to-use memory controller simplifies memory designs by supporting 100, 133, 167, 200, 267, and 300 MHz. SDR, DDR, DDR2, and mobile DDR memory devices use a single Avalon system interconnect. A proprietary source-synchronous data synchronization design feature enables maximum system clock rates using low-speed FPGAs and standard-memory devices.
The SDRAM memory controller has up to ten Avalon ports. For example, you can use the first port for processor instruction and data words. The other ports can serve as interfaces for video and audio data or can simply be disabled. You can configure each port for:
Avalon random slave
Avalon streaming slave
Avalon pipelined burst
The ports use a round-robin bus arbitration system.
By using a multi-port memory controller, you can partition the Avalon system bus architecture of the system-on-a-chip (SoC) design and optimize the performance of each sub-system. Each port is supported with a data FIFO/cache which effectively doubles memory bandwidth over traditional single cache SDRAM IP cores. You can tailor FIFO/cache depth for either streaming or random access.
The core handles all memory tasks, including initialization and refresh cycles. Since the SDRAM controller is designed to operate asynchronous of the system clocks, you can clock the SDRAM devices at their peak rated frequency, maximizing performance.
The Avalon Multi-Port SDRAM Memory Controller core uses a proprietary source-synchronous clocking technology to improve the capture of SDRAM data. By making data capture independent of a phase-locked loop (PLL) system clock, timing margins are relaxed, increasing memory performance to 200 and 333 MHz in Cyclone II and Cyclone III and Stratix II and Stratix III FPGAs. This unique source-synchronous clocking technique also frees the IP core design task from the PCB design step and reduces the FPGA design compilation to a simple two-step process.
You can easily customize the core for bus data width or other arbitrations schemes, additional system ports can be supported, and source code is available for purchase.
The core is optimized for Altera® Cyclone, Arria® GX, and Stratix families of programmable logic devices and supplied as a SOPC Builder Ready component for ease of configuration.
Device Utilization Examples
Table 1 lists the typical device utilization results for the Avalon Multi-Port SDRAM Memory Controller.