RLDRAM II Controller Intel® FPGA IP Core

  • Support for industry-standard RLDRAM II components
    • Common I/O (CIO) and separate I/O (SIO) device support
  • Flexible and robust design
    • Non-multiplexed addressing
    • Datapath generation
    • Data strobe signal (DQS) and non-DQS capture modes
    • Intellectual property (IP) functional simulation models for use in Intel FPGA-supported VHDL and Verilog HDL simulators
    • Easy-to-use IP Toolbench interface and automatic constraint generation

Typical expected performance and utilization figures for this Intel FPGA IP function are provided in the RLDRAM II Controller Intel FPGA IP Function User Guide (PDF).

For technical support on this Intel FPGA IP function, please visit Intel Premier Support. You may also search for related topics on this function in the Knowledge Database.