RLDRAM II Controller Intel® FPGA IP

  • Support for industry-standard RLDRAM II components
    • Common I/O (CIO) and separate I/O (SIO) device support
  • Flexible and robust design
    • Non-multiplexed addressing
    • Datapath generation
    • Data strobe signal (DQS) and non-DQS capture modes
    • Intellectual property (IP) functional simulation models for use in Intel FPGA-supported VHDL and Verilog HDL simulators
    • Easy-to-use IP Toolbench interface and automatic constraint generation

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