The Intel® FPGA intellectual property (IP) for DDR and DDR2 SDRAM High-Performance Controller provides simplified interfaces to industry-standard DDR SDRAM and DDR2 SDRAM. The Intel FPGA IP work in conjunction with the Intel FPGA ALTMEMPHY physical interface IP. The controllers offer a half-rate interface and a full-rate interface to the customer application logic. For exact device support, please refer to the user guide.
The parameter editor generates a design example, instantiates a phase-locked loop (PLL), an example driver, your DDR or DDR2 SDRAM controller custom variation, and an optional delay-locked loop (DLL) (for Stratix® series FPGAs only). The design example is a fully functional design that can be simulated, synthesized, and used in hardware. The example driver is a self-test module that issues read and write commands to the controller and checks the read data to produce the pass/fail and test complete signals.