The High-Performance Memory Controller II SDRAM Intel® FPGA IP core handles the complex aspects of using DDR, DDR2, and DDR3 SDRAM at speeds up to 933 MHz. The intellectual property (IP) core initializes the memory devices, manages SDRAM banks, translates read-and-write requests from the local interface into all the necessary SDRAM command signals, and performs command and data reordering.
The High-Performance Memory Controller II SDRAM Intel FPGA IP core is a drop-in replacement for the existing SDRAM controller with the following new enhanced features:
2-T command timing to maintain command channel bandwidth
50 percent higher random access efficiency with command and data reordering†
Power-down and self-refresh support
Error correction code (ECC) with sub-word writes
This IP is included in the IP Base Suite which is bundled with Intel® Quartus® Prime Standard and Pro Edition Software.