DDR and DDR2 SDRAM Controller Intel® FPGA IP Core

The DDR and DDR2 SDRAM controllers handle the complex aspects of using DDR and DDR2 SDRAM—initializing the memory devices, managing SDRAM banks, and keeping the devices refreshed at appropriate intervals. The controllers translate read-and-write requests from the local interface into all the necessary SDRAM command signals.

Whether you use the intellectual property (IP) Toolbench in the Platform Designer (formerly Qsys) or the Intel® Quartus® Prime design software, it generates a design example, instantiates a phase-locked loop (PLL), an example driver, and your DDR/DDR2 SDRAM controller custom variation. The design example is a fully-functional example design that can be simulated, synthesized, and used in hardware. The example driver is a self-test module that issues read-and-write commands to the controller and checks the read data to produce the pass/fail and test complete signals.

You can replace the DDR/DDR2 SDRAM controller encrypted control logic in the example instance with your own custom logic, which allows you to use the Intel FPGA clear-text datapath with your own control logic.

  • Support for industry-standard DDR and DDR2 SDRAM devices and modules
    • Including support for registered DIMMs
  • Flexible, robust design
    • 1, 2, 4, or 8 chip-select signals
    • Configurable data width including data strobe (DQS) read postamble control logic and optional non-DQS read mode for side banks (Stratix® series FPGAs)
    • Automatic or user-controlled refresh
    • Data mask signals for partial write operations
    • Bank management architecture, which minimizes latency
  • Quick and easy implementation
    • IP Toolbench-generated constraint script
    • Top-level example design shipped as a deliverable with the Intel FPGA IP function
    • IP functional simulation models used in Intel® FPGA-supported VHDL and Verilog HDL simulators
    • Free clear-text datapath for use with custom controller
  • Platform Designer (formerly Qsys) IP-ready to enable system-level design

Typical expected performance and utilization figures for this Intel® FPGA IP function are provided in the DDR and DDR2 SDRAM Controller Compiler User Guide (PDF).

For technical support on this Intel® FPGA IP function, please visit Intel Premier Support. You may also search for related topics on this function in the Knowledge Center.