The DDR and DDR2 SDRAM controllers handle the complex aspects of using DDR and DDR2 SDRAM—initializing the memory devices, managing SDRAM banks, and keeping the devices refreshed at appropriate intervals. The controllers translate read-and-write requests from the local interface into all the necessary SDRAM command signals.
Whether you use the intellectual property (IP) Toolbench in the Platform Designer (formerly Qsys) or the Intel® Quartus® Prime design software, it generates a design example, instantiates a phase-locked loop (PLL), an example driver, and your DDR/DDR2 SDRAM controller custom variation. The design example is a fully-functional example design that can be simulated, synthesized, and used in hardware. The example driver is a self-test module that issues read-and-write commands to the controller and checks the read data to produce the pass/fail and test complete signals.
You can replace the DDR/DDR2 SDRAM controller encrypted control logic in the example instance with your own custom logic, which allows you to use the Intel FPGA clear-text datapath with your own control logic.