Embedded USB 3.0 Device Controller

  • USB 3.0 compatible link for embedded applications
  • Implementation of PHY Layer (with Altera 5+ Gbps transceiver), Link Layer and Protocol Layer
  • Supports CONTROL, BULK and ISO transfer without stream support
  • Supports 32-bit PHY Layer data interface between Altera Transceiver PHY IP core and Link Layer
  • Configurable Endpoint selection
  • Option for USB 2.0 compatible link with external USB 2.0 PHY

Figure 2. Block Diagram Device Controller

Supported Devices and Resource Counts

Device LE Memory Bits Memory Blocks
Arria V GX / GT / GZ / SX SoC / ST SoC ~ 15K ~ 300,000 47 x M10K
Cyclone V GT / ST SoC ~ 15K ~ 300,000 44 x M10K
Stratix V GX / GS / GT ~ 16K ~ 300,000 44 x M20K

USB 3.0 Four Pin Chip-to-Chip Connectivity

Learn about Altera’s Embedded USB 3.0 Device Controller solution, and how it can simplify your design of chip-to-chip USB 3.0 connectivity.

For additional information, contact SLS at:

US Office
System Level Solutions Inc.
14100 Murphy Ave.
San Martin, CA 95046
Phone: (408) 852-0067
Fax: (408) 856-2469
Email: info@slscorp.com
URL: http://www.slscorp.com

India Office
System Level Solutions India Pvt. Ltd.
Plot #32, Zone-D/4,
Phase-1, GIDC Estate,
V.U. Nagar - 388 121
Gujarat 388121, India
Phone: +91 (2692) 232501 or 232502 / +1 (408) 705-2399
Email: info@slscorp.com
URL: http://www.slscorp.com