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PCIe Intel® FPGA IP

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Intel® Agilex™ FPGA PCIe* Gen4 x16 Demo

PCIe and Intel Technology

PCI Express* (PCIe*) protocol is a high-performance, scalable, and feature-rich serial protocol with data transfer rates from 2.5 gigatransfers per second (GT/s) to 16.0 GT/s and beyond. Intel offers a unique combination of hardened and soft IP to provide superior performance and flexibility for optimal integration.

  • PCI Express hardened protocol stack (transaction and data link layers)
  • Hardened physical layer (physical medium attachment and physical coding sublayer)
  • Optional soft/hard logic blocks (DMA engines and single-root I/O virtualization)
  • Feature support for VirtIO, ScalableIO, and Shared Virtual Memory
  • PCIe Express Multichannel DMA IP available to complement P-tile/H-tile PCI Express Hard IP
  • PCIe Express Scalable Switch IP available to complement P-tile PCIe Express Hard IP
Contact Intel Sales PCIe Support Center IP Evaluation and Purchase

Features

 

Intel® FPGA Intellectual Property (IP) for PCI Express continues to scale as the PCI-SIG organization delivers next-generation specifications. Intel has been a member of PCI-SIG since 1992, and with each new generation of silicon, Intel continues to participate in PCI-SIG Compliance Workshops to ensure interoperability and conformance with current industry standards.

Intel offers FPGA IP function-based PCI Express IP solutions that are compliant with the Platform Designer.

P-Tile PCIe Hard IP successfully passed August ‘19 PCI-SIG Compliance Testing Event. Results posted on the PCI-SIG integrators webpage.

 

PCIe* Features for P-Tile Hard IP:

  • Complete protocol stack including the transaction, data link, and physical layers implemented as a Hard IP
  • Natively supports up to Gen4x16 for endpoint and root port modes
  • Port bifurcation capabilities: four x4s root port, two x8s endpoint
  • Supports TLP bypass mode in both upstream and downstream modes
  • Supports up to 512B maximum payload
  • 10 bit tag support for x16 controller only with maximum 512 outstanding NPRs
  • Separate Refclk with independent spread spectrum Clocking (SRIS)
    • Separate Refclk with no spread spectrum clocking (SRNS)
    • Common Refclk architecture
  • PCI Express advanced error reporting (PF only)
  • Supports D0 and D3 PCIe power states only
  • Lane margining at receiver
  • Retimers presence detection


Multifunction and Virtualization Features:

  • SR-IOV support (8 PFs, 2K VFs per each Endpoint)
  • VirtIO support via configuration intercept interface
  • Scalable I/O and shared virtual memory (SVM) support (future)
  • Access control service (ACS)
  • Alternative routing-ID interpretation (ARI)
  • Function level reset (FLR)
  • TLP processing hint (TPH)
  • Address Translation Services (ATS)
  • Process address space ID (PasID)


User Interface Features:

  • Avalon® streaming (Avalon-ST) /Avalon memory-mapped (Avalon-MM) user-side interfaces
  • User packet interface with separate header, data and prefix
  • User packet interface can handle up to two TLPs in any given cycle (x16 mode only)
  • Up to 512 outstanding non-posted requests (x16 core only)
  • Up to 256 outstanding non-posted requests (x8 and x4 cores)
  • Supports autonomous Hard IP mode
    • This mode allows the PCIe Hard IP to communicate with the Host before the FPGA configuration and entry into user mode are complete.
  • FPGA core configuration via PCIe link (CVP Init and CVP Update) 


IP Debug Features:

  • Debug toolkit including the following features:
    • Protocol and link status information
    • Basic and advanced debugging capabilities including PMA register access and Eye viewing capability.


Driver Support:

  • Linux*/Windows* device drivers

Table 1. Device Support and Number of Hardened PCI Express IP Blocks

Device Family Number of Hardened PCI Express* IP Blocks PCI Express Link Speed    

Gen1

(2.5 GT/s)

Gen2

(5.0 GT/s)

Gen3

(8.0 GT/s)

Gen4

(16.0 GT/s)

Gen5

(32.0 GT/s)
Intel® Agilex™ 1 to 3 per device  ✓ ✓ ✓ ✓ ✓
Intel® Stratix® 10 1 to 4 per device ✓ ✓ ✓ ✓  
Intel® Arria® 10 1 to 4 per device ✓ ✓ ✓    
Intel® Cyclone® 10 1 per device ✓ ✓      
Stratix® V 1 to 4 per device ✓ ✓ ✓    
Arria® V 1 or 2 per device ✓ ✓      
Intel® Cyclone® 10 GX 1 per device  ✓ ✓      
Cyclone® V GT 2 per device ✓ ✓      
Cyclone® V GX 1 or 2 per device ✓        
Stratix® IV 2 to 4 per device ✓ ✓      
Cyclone® IV GX 1 per device ✓        
Arria® II GZ 1 per device ✓ ✓      
Arria® II GX 1 per device ✓        

Table 2. Device Configurations and Features Support

Interface Type Avalon®-ST Avalon-MM Avalon-MM with DMA SR-IOV CvP / PRoP
Device/Configuration  
Intel® Agilex™ Endpoint Up to Gen4 x16 Up to Gen4 x16 Up to Gen4 x16 Available Up to Gen4 x16: CvP Init
Root Port Up to Gen4 x16 Up to Gen4 x16 - - -
Intel® Stratix® 10 Endpoint Up to Gen4 x16 Up to Gen4 x16 Up to Gen4 x16 Available Up to Gen4 x16: CvP Init
Root Port Up to Gen4 x16 Up to Gen4 x16 - - -
Intel® Arria® 10 Endpoint Up to Gen3 x8 Up to Gen3 x4 Gen1 x8, Gen2 x4, Gen2 x8, Gen3 x2, Gen3 x4, Gen3 x8 Available Up to Gen3 x8: CvP and PRoP
Root Port Up to Gen3 x8 Up to Gen3 x4 - - -
Intel® Cyclone® 10 GX Endpoint Up to Gen2 x4 Up to Gen2 x4 Gen2 x4 - Up to Gen2 x4: CvP and PRoP
Root Port Up to Gen2 x4 Up to Gen2 x4 - - -
Stratix® V Endpoint Up to Gen3 x8 Up to Gen3 x4 Gen1 x8, Gen2 x4, Gen2 x8
Gen3 x2, Gen3 x4, Gen3 x8		 Available Gen1: CvP Init and CvP Update
Gen2: CvP Init and CvP Update
Root Port Up to Gen3 x8 Up to Gen3 x4 - - -
Arria® V GZ Endpoint Up to Gen3 x8 Up to Gen3 x4 Gen1 x8, Gen2 x4, Gen2 x8
Gen3 x2, Gen3 x4, Gen3 x8		 - Gen1: CvP Init and CvP Update
Gen2: CvP Init and CvP Update
Root Port Up to Gen3 x8 Up to Gen3 x4 - - -
Arria® V Endpoint Up to Gen1 x8 and Gen2 x4

Up to Gen1 x8 and

Gen2 x4 (no x2)

 Gen1 x8, Gen2 x4 - Up to Gen1 x8 and Gen2 x4
Gen1: CvP Init and CvP Update
Gen2: CvP Init
Root Port Up to Gen1 x8 and Gen2 x4

Up to Gen1 x8 and

Gen2 x4 (no x2)

 - - -
Cyclone® V Endpoint Up to Gen2 x4 Up to Gen2 x4 (no x2) Gen2 x4 - Up to Gen2 x4
Gen1: CvP Init and CvP Update
Gen2: CvP Init
Root Port Up to Gen2 x4 Up to Gen2 x4 (no x2) - - -
  • CvP – Configuration via Protocol
  • PRoP – Partial Reconfiguration over PCI Express
  • SR-IOV – Single Root I/O Virtualization
  • DMA – Direct Memory Access

IP Quality Metrics

Basics

Year IP was first released

2005

Latest version of Intel® Quartus® Prime software supported

20.2

Status

Production

Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Timing and/or layout constraints
  • Documentation with revision control
 Y for all, except for providing Readme files

Any additional customer deliverables provided with IP

Testbench and design examples

Parameterization GUI allowing end user to configure IP

Y

IP core is enabled for Intel® FPGA IP Evaluation Mode Support 

Y

Source language

Verilog

Testbench language

Verilog

Software drivers provided

Y

Driver OS Support

Linux/Windows

Implementation

User interface

Avalon® Streaming, Avalon Memory-Mapped

IP-XACT metadata

N

Verification

Simulators supported

NCSim, ModelSim, VCS

Hardware validated

Intel® Arria® 10, Intel® Stratix® 10

Industry standard compliance testing performed

Y

If Yes, which test(s)?

PCI-SIG

If Yes, on which Intel FPGA device(s)?

 Intel Stratix 10 GX L-Tile, Intel Stratix 10 GX H-Tile, Intel Stratix 10 DX P-Tile

If Yes, date performed

Aug 2019 (Intel Stratix 10 FPGA P-Tile)

If No, is it planned?

N/A

Interoperability

IP has undergone interoperability testing

Y

If yes, on which Intel FPGA device(s)

 Intel Stratix 10 GX L-Tile/H-Tile, Intel Stratix 10 DX P-Tile

Interoperability reports available

Y

Documentation

 
  • PCI Express IP Support Center
  • Intel FPGA IP PCI Express Online Training

Intel® Stratix® 10 DX FPGA Features Demo


Intel® Stratix® 10 FPGA PCI Express* Gen3x16 SR-IOV


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For technical support on this IP core, please visit the PCI Express IP Support Center. You can also search for related topics on this function in the Knowledge Center.

  • Intel FPGA IP Release Notes
  • Designing with Intel FPGA Intellectual Property
  • I-Tested
  • Qsys-Compliant Certification
  • Protocol Standard
    • PCI-SIG website
    • PCI-SIG Integrators List

† Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase.  For more complete information about performance and benchmark results, visit www.intel.com/benchmarks.

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