Intel® FPGA IP for PCI Express*

Intel® Stratix® 10 PCI Express* Gen3x16 SR-IOV

PCI Express Link Inspector Demo

Automated Generation of SignalTap II Files for Arria® 10 IP Core Debug

PCI Express* (PCIe*) protocol is a high-performance, scalable, and feature-rich serial protocol with data transfer rates from 2.5 gigatransfers per second (GT/s) to 8.0 GT/s and beyond. Intel^® FPGA Intellectual Property (IP) for PCI Express continues to scale as the PCI-SIG* organization delivers next-generation specifications. Intel has been a member of PCI-SIG since 1992, and with each new generation of silicon, Intel continues to participate in PCI-SIG Compliance Workshops to ensure interoperability and conformance with current industry standards.

The PCI Express IP solutions include Intel’s technology-leading PCI Express hardened protocol stack, which includes the transaction and data link layers, and hardened physical layer, which includes both the physical medium attachment (PMA) and physical coding sublayer (PCS). Intel's PCI Express IP also includes optional soft logic blocks, such as direct memory access (DMA) engines and single-root I/O virtualization (SR-IOV). This unique combination of hardened and soft IP provides superior performance and flexibility for optimal integration.

Intel offers Intel FPGA IP function-based PCI Express IP solutions that are compliant with the Platform Designer (formerly Qsys). For more information, please contact your local Intel FPGA sales representative.

Features

New hardened protocol stack on Intel^® Stratix^® 10 device
- Intel Stratix 10 device: 14 nm Intel Tri-Gate (FinFET) process
4th generation hardened protocol stack, PCS, and PMA layers
- Four device generations
  - (65 nm, 40 nm, 28 nm, 20 nm)
- Seven product families
Direct memory access (DMA) engine and device drivers built for best performance and efficiency
- Highest throughput and input/output operations per second (IOPS) performance
  - Up to 6.8 gigabytes per second (GBps) of throughput and greater than 500K IOPS
- Scatter-gather-based DMA
- Linux* and Windows* device drivers
  - Character and block device driver support
  - Open source code
  - License model is dual BSD/GPL
Gen1, Gen2, Gen3 support
x1, x2, x4, x8 lane widths (x16 lane width on the Intel Stratix 10 device)
Root port and endpoint configurations
SR-IOV feature
- Four physical functions (PFs) / 2048 virtual functions (VFs)
- MSI / MSI-X interrupt support
Configuration via protocol (PCIe) initialization (CvP Init) and update (CvP Update)
- For power-up programming
Partial reconfiguration over protocol (PCIe) (PRoP)
- For multiple image programming while powered
Multiple user interface options
- Avalon^® Streaming (Avalon-ST)
- Avalon Memory-Mapped (Avalon-MM)
- Avalon-MM with DMA

Device Support

Table 1. Device Support and Number of Hardened PCI Express IP Blocks

Device Family	*Number of Hardened PCI Express IP Blocks**	PCI Express Link Speed
Device Family	*Number of Hardened PCI Express IP Blocks**	Gen1 (2.5 GT/s)	Gen2 (5.0 GT/s)	Gen3 (8.0 GT/s)
Intel® Stratix® 10	1 to 4 per device
Intel® Arria®10	1 to 4 per device
Intel Cyclone® 10	1 per device
Stratix V	1 to 4 per device
Arria V	1 or 2 per device
Intel Cyclone 10 GX	1 per device
Cyclone V GT	2 per device
Cyclone V GX	1 or 2 per device
Stratix IV	2 to 4 per device
Cyclone IV GX	1 per device
Arria II GZ	1 per device
Arria II GX	1 per device

Table 2. Device Configurations and Features Support

Interface Type		Avalon-ST	Avalon-MM	Avalon-MM with DMA	SR-IOV	CvP / PRoP
Device/Configuration
Intel Stratix 10	Endpoint	Up to Gen3 x16	Up to Gen3 x8	Up to Gen3 x8	Available	Up to Gen3 x16: CvP Init
Intel Stratix 10	Root Port	Up to Gen3 x8	Up to Gen3 x8	-	-	-
Intel Arria 10	Endpoint	Up to Gen3 x8	Up to Gen3 x4	Gen1 x8, Gen2 x4, Gen2 x8, Gen3 x2, Gen3 x4, Gen3 x8	Available	Up to Gen3 x8: CvP and PRoP
Intel Arria 10	Root Port	Up to Gen3 x8	Up to Gen3 x4	-	-	-
Intel Cyclone 10 GX	Endpoint	Up to Gen2 x4	Up to Gen2 x4	Gen2 x4	-	Up to Gen2 x4: CvP and PRoP
Intel Cyclone 10 GX	Rootport	Up to Gen2 x4	Up to Gen2 x4	-	-	-
Stratix V	Endpoint	Up to Gen3 x8	Up to Gen3 x4	Gen1 x8, Gen2 x4, Gen2 x8 Gen3 x2, Gen3 x4, Gen3 x8	Available	Gen1: CvP Init and CvP Update Gen2: CvP Init and CvP Update
Stratix V	Root Port	Up to Gen3 x8	Up to Gen3 x4	-	-	-
Arria V GZ	Endpoint	Up to Gen3 x8	Up to Gen3 x4	Gen1 x8, Gen2 x4, Gen2 x8 Gen3 x2, Gen3 x4, Gen3 x8	-	Gen1: CvP Init and CvP Update Gen2: CvP Init and CvP Update
Arria V GZ	Root Port	Up to Gen3 x8	Up to Gen3 x4	-	-	-
Arria V	Endpoint	Up to Gen1 x8 and Gen2 x4	Up to Gen1 x8 and Gen2 x4 (no x2)	Gen1 x8, Gen2 x4	-	Up to Gen1 x8 and Gen2 x4 Gen1: CvP Init and CvP Update Gen2: CvP Init
Arria V	Root Port	Up to Gen1 x8 and Gen2 x4	Up to Gen1 x8 and Gen2 x4 (no x2)	-	-	-
Cyclone V	Endpoint	Up to Gen2 x4	Up to Gen2 x4 (no x2)	Gen2 x4	-	Up to Gen2 x4 Gen1: CvP Init and CvP Update Gen2: CvP Init
Cyclone V	Root Port	Up to Gen2 x4	Up to Gen2 x4 (no x2)	-	-	-

IP Quality Metrics

Table 3. PCI Express* IP Quality Metrics

Basics
Year IP was first released	2005
Latest version of Intel® Quartus^® Prime Design Software supported	18.1
Status	Production
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim*- Intel FPGA Edition Timing and/or layout constraints Documentation with revision control Readme file	Y for all, except for providing Readme files
Any additional customer deliverables provided with IP	Testbench and design examples
Parameterization GUI allowing end user to configure IP	Y
IP core is enabled for Intel FPGA IP Evaluation Mode Support	Y
Source language	Verilog and VHDL
Testbench language	Verilog
Software drivers provided	Y
Driver OS Support	Linux/Windows
Implementation
User interface	Avalon® Streaming, Avalon Memory-Mapped
IP-XACT metadata	N
Verification
Simulators supported	NCSim, ModelSim*, VCS/VCSMX
Hardware validated	Intel Arria® 10, Intel Stratix® 10
Industry standard compliance testing performed	Y
If Yes, which test(s)?	PCI-SIG*
If Yes, on which Intel FPGA device(s)?	Intel Stratix 10 GX L-Tile
If Yes, date performed	December 2017
If No, is it planned?	N/A
Interoperability
IP has undergone interoperability testing	Y
If yes, on which Intel FPGA device(s)	Intel Stratix 10 GX L-Tile
Interoperability reports available	Y

Reference Designs

Intel offers a host of PCIe* reference designs and application notes. These reference designs and application notes offer ready-made solutions that can be leveraged for feasibility studies, device selections, and design proofing on Intel^® FPGAs and SoCs.

The Intel FPGA development kits complement the reference designs and application notes by delivering a complete system-level design environment that includes both the hardware and software needed to immediately begin developing designs. Each reference design indicates which Intel FPGA development kit and version of the Intel Quartus^® software (version 15.1 and above) software were used for its development cycle.

As PCIe is a very configurable IP solution and supports numerous application needs, we cannot offer reference designs for every configuration or application possible. If there is no readily available reference design for your particular configuration or device, you may use a similar design and modify and/or port it as needed to fit your design requirements.

Reference designs are available on the new PCI Express IP Support Center.

Technical Support

For technical support on this Intel^® FPGA IP function, please visit PCI Express-Support Center. You may also search for related topics on this function in the Knowledge Database.