Intel® FPGA IP for PCI Express*

Figure 1. PCI Express* Block Diagram

Intel® Stratix® 10 PCI Express* Gen3x16 SR-IOV 


PCI Express Link Inspector Demo


Automated Generation of SignalTap II Files for Arria® 10 IP Core Debug


PCI Express* (PCIe*) protocol is a high-performance, scalable, and feature-rich serial protocol with data transfer rates from 2.5 gigatransfers per second (GT/s) to 16.0 GT/s and beyond. Intel® FPGA Intellectual Property (IP) for PCI Express continues to scale as the PCI-SIG* organization delivers next-generation specifications. Intel has been a member of PCI-SIG since 1992, and with each new generation of silicon, Intel continues to participate in PCI-SIG Compliance Workshops to ensure interoperability and conformance with current industry standards.

The PCI Express IP solutions include Intel’s technology-leading PCI Express hardened protocol stack, which includes the transaction and data link layers, and hardened physical layer, which includes both the physical medium attachment (PMA) and physical coding sublayer (PCS). Intel's PCI Express IP also includes optional soft/hard logic blocks, such as direct memory access (DMA) engines and single-root I/O virtualization (SR-IOV). The latest versions of the hard IP core on P-tile also include feature support for VirtIO, ScalableIO and Shared Virtual Memory. This unique combination of hardened and soft IP provides superior performance and flexibility for optimal integration.

Intel offers Intel FPGA IP function-based PCI Express IP solutions that are compliant with the Platform Designer (formerly Qsys). For more information, please contact your local Intel FPGA sales representative.

PCIe* Features for P-tile Hard IP:

  • Complete protocol stack including the Transaction, Data Link, and Physical Layers implemented as a Hard IP
  • Natively supports up to Gen4 x16 for Endpoint and Rootport modes
  • Port bifurcation capabilities: four x4s Root Port, two x8s Endpoint
  • Supports TLP Bypass mode in both Upstream and Downstream modes
  • Supports up to 512B maximum payload
  • 10-bit Tag Support for x16 Controller only with Maximum 512 Outstanding NPRs
  • Separate Refclk with Independent Spread Spectrum Clocking (SRIS)
    • Separate Refclk with no Spread Spectrum Clocking (SRNS)
    • Common Refclk architecture
  • PCI ExpressAdvanced Error Reporting (PF only)
  • Supports D0 and D3 PCIe power states only
  • Lane Margining at Receiver
  • Retimers presence detection

Multifunction and Virtualization Features:

  • SR-IOV support (8 PFs, 2K VFs per each Endpoint)
  • VirtIO Support via Configuration Intercept Interface
  • Scalable IO and Shared Virtual Memory (SVM)* Support (future)
  • Access Control Service(ACS)
  • Alternative Routing-ID Interpretation (ARI)
  • Function Level Reset(FLR)
  • TLP Processing Hint (TPH)
  • Address Translation Services (ATS)
  • Process Address Space ID (PasID)

User Interface Features:

  • AVST / AVMM User-side interfaces
  • User packet interface with separate header, data and prefix
  • User packet interface can handle up to 2 TLPs in any given cycle (x16 mode only)
  • Up to 512 outstanding Non-Posted requests (x16 core only)
  • Up to 256 outstanding Non-Posted requests (x8 and x4 cores)
  • Supports Autonomous Hard IP mode
    • This mode allows the PCIe Hard IP to communicate with the Host before the FPGA configuration and entry into User mode are complete.
  • FPGA core configuration via PCIe link (CVP Init and CVP Update) 

IP Debug Features:

  • Debug toolkit including the following features:
    • Protocol and link status information
    • Basic and advanced debugging capabilities including PMA register access and Eye viewing capability.

Driver Support:

  • Linux/Windows device drivers

Table 1. Device Support and Number of Hardened PCI Express IP Blocks

Device Family Number of Hardened PCI Express* IP Blocks PCI Express Link Speed    

Gen1

(2.5 GT/s)

Gen2

(5.0 GT/s)

Gen3

(8.0 GT/s)

Gen4

(16.0 GT/s)

Gen5

(32.0 GT/s)

Intel® Agilex® 1 to 3 per device  check mark check mark check mark check mark check mark
Intel® Stratix® 10 1 to 4 per device check mark check mark check mark check mark  
Intel® Arria® 10 1 to 4 per device check mark check mark check mark    
Intel Cyclone® 10 1 per device check mark check mark      
Stratix V 1 to 4 per device check mark check mark check mark    
Arria V 1 or 2 per device check mark check mark      
Intel Cyclone 10 GX 1 per device  check mark check mark      
Cyclone V GT 2 per device check mark check mark      
Cyclone V GX 1 or 2 per device check mark        
Stratix IV 2 to 4 per device check mark check mark      
Cyclone IV GX 1 per device check mark        
Arria II GZ 1 per device check mark check mark      
Arria II GX 1 per device check mark        

Table 2. Device Configurations and Features Support

Interface Type Avalon-ST Avalon-MM Avalon-MM with DMA SR-IOV CvP / PRoP
Device/Configuration  
Intel Stratix 10 Endpoint Up to Gen3 x16 Up to Gen3 x8 Up to Gen3 x8 Available Up to Gen3 x16: CvP Init
Root Port Up to Gen3 x8 Up to Gen3 x8 - - -
Intel Arria 10 Endpoint Up to Gen3 x8 Up to Gen3 x4 Gen1 x8, Gen2 x4, Gen2 x8, Gen3 x2, Gen3 x4, Gen3 x8 Available Up to Gen3 x8: CvP and PRoP
Root Port Up to Gen3 x8 Up to Gen3 x4 - - -
Intel Cyclone 10 GX Endpoint Up to Gen2 x4 Up to Gen2 x4 Gen2 x4 - Up to Gen2 x4: CvP and PRoP
Rootport Up to Gen2 x4 Up to Gen2 x4 - - -
Stratix V Endpoint Up to Gen3 x8 Up to Gen3 x4 Gen1 x8, Gen2 x4, Gen2 x8
Gen3 x2, Gen3 x4, Gen3 x8
Available Gen1: CvP Init and CvP Update
Gen2: CvP Init and CvP Update
Root Port Up to Gen3 x8 Up to Gen3 x4 - - -
Arria V GZ Endpoint Up to Gen3 x8 Up to Gen3 x4 Gen1 x8, Gen2 x4, Gen2 x8
Gen3 x2, Gen3 x4, Gen3 x8
- Gen1: CvP Init and CvP Update
Gen2: CvP Init and CvP Update
Root Port Up to Gen3 x8 Up to Gen3 x4 - - -
Arria V Endpoint Up to Gen1 x8 and Gen2 x4

Up to Gen1 x8 and

Gen2 x4 (no x2)

Gen1 x8, Gen2 x4 - Up to Gen1 x8 and Gen2 x4
Gen1: CvP Init and CvP Update
Gen2: CvP Init
Root Port Up to Gen1 x8 and Gen2 x4

Up to Gen1 x8 and

Gen2 x4 (no x2)

- - -
Cyclone V Endpoint Up to Gen2 x4 Up to Gen2 x4 (no x2) Gen2 x4 - Up to Gen2 x4
Gen1: CvP Init and CvP Update
Gen2: CvP Init
Root Port Up to Gen2 x4 Up to Gen2 x4 (no x2) - - -

Table 3. PCI Express* IP Quality Metrics

Basics

Year IP was first released

2005

Latest version of Intel® Quartus® Prime Design Software supported

18.1

Status

Production

Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim*- Intel FPGA Edition
  • Timing and/or layout constraints
  • Documentation with revision control
  • Readme file
Y for all, except for providing Readme files

Any additional customer deliverables provided with IP

Testbench and design examples

Parameterization GUI allowing end user to configure IP

Y

IP core is enabled for Intel FPGA IP Evaluation Mode Support 

Y

Source language

Verilog and VHDL

Testbench language

Verilog

Software drivers provided

Y

Driver OS Support

Linux/Windows

Implementation

User interface

Avalon® Streaming, Avalon Memory-Mapped

IP-XACT metadata

N

Verification

Simulators supported

NCSim, ModelSim*, VCS/VCSMX

Hardware validated

Intel Arria® 10, Intel Stratix® 10

Industry standard compliance testing performed

Y

If Yes, which test(s)?

PCI-SIG*

If Yes, on which Intel FPGA device(s)?

Intel Stratix 10 GX L-Tile

If Yes, date performed

December 2017

If No, is it planned?

N/A

Interoperability

IP has undergone interoperability testing

Y

If yes, on which Intel FPGA device(s)

Intel Stratix 10 GX L-Tile

Interoperability reports available

Y

Intel offers a host of PCIe* reference designs and application notes. These reference designs and application notes offer ready-made solutions that can be leveraged for feasibility studies, device selections, and design proofing on Intel® FPGAs and SoCs.

The Intel FPGA development kits complement the reference designs and application notes by delivering a complete system-level design environment that includes both the hardware and software needed to immediately begin developing designs. Each reference design indicates which Intel FPGA development kit and version of the Intel Quartus® software (version 15.1 and above) software were used for its development cycle.

As PCIe is a very configurable IP solution and supports numerous application needs, we cannot offer reference designs for every configuration or application possible. If there is no readily available reference design for your particular configuration or device, you may use a similar design and modify and/or port it as needed to fit your design requirements. 

 

Reference designs are available on the new PCI Express IP Support Center.  

 

For technical support on this Intel® FPGA IP function, please visit PCI Express-Support Center. You may also search for related topics on this function in the Knowledge Database.

† Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase.  For more complete information about performance and benchmark results, visit www.intel.com/benchmarks.

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