... PCI Express IP

Intel® FPGA IP for PCI Express

Intel® Stratix® 10 DX FPGA Features Demo

Intel® Agilex™ FPGA PCIe* Gen4 x16 Demo

Intel® Stratix® 10 FPGA PCI Express* Gen3x16 SR-IOV

PCI Express* (PCIe*) protocol is a high-performance, scalable, and feature-rich serial protocol with data transfer rates from 2.5 gigatransfers per second (GT/s) to 16.0 GT/s and beyond. Intel^® FPGA intellectual property (IP) for PCI Express continues to scale as the PCI-SIG organization delivers next-generation specifications. Intel has been a member of PCI-SIG since 1992, and with each new generation of silicon, Intel continues to participate in PCI-SIG Compliance Workshops to ensure interoperability and conformance with current industry standards.

The PCI Express IP solutions include Intel’s technology-leading PCI Express hardened protocol stack, which includes the transaction and data link layers, and hardened physical layer, which includes both the physical medium attachment (PMA) and physical coding sublayer (PCS). Intel's PCI Express IP also includes optional soft/hard logic blocks, such as direct memory access (DMA) engines and single-root I/O virtualization (SR-IOV). The latest versions of the hard IP core on P-tile also include feature support for VirtIO, ScalableIO and Shared Virtual Memory. This unique combination of hardened and soft IP provides superior performance and flexibility for optimal integration.

Intel offers Intel FPGA IP function-based PCI Express IP solutions that are compliant with the Platform Designer.

P-Tile PCIe Hard IP successfully past August ‘19 PCI-SIG Compliance Testing Event. Results posted on the PCI-SIG integrators webpage.

For more information, please contact your local Intel FPGA sales representative.

Features

PCIe* Features for P-Tile Hard IP:

Complete protocol stack including the transaction, data link, and physical layers implemented as a Hard IP
Natively supports up to Gen4 x16 for endpoint and rootport modes
Port bifurcation capabilities: four x4s root port, two x8s endpoint
Supports TLP bypass mode in both upstream and downstream modes
Supports up to 512B maximum payload
10 bit tag support for x16 controller only with maximum 512 outstanding NPRs
Separate Refclk with independent spread spectrum Clocking (SRIS)
- Separate Refclk with no spread spectrum clocking (SRNS)
- Common Refclk architecture
PCI Express advanced error reporting (PF only)
Supports D0 and D3 PCIe power states only
Lane margining at receiver
Retimers presence detection

Multifunction and Virtualization Features:

SR-IOV support (8 PFs, 2K VFs per each Endpoint)
VirtIO support via configuration intercept interface
Scalable I/O and shared virtual memory (SVM) support (future)
Access control service (ACS)
Alternative routing-ID interpretation (ARI)
Function level reset (FLR)
TLP processing hint (TPH)
Address translation services (ATS)
Process address space ID (PasID)

User Interface Features:

Avalon® streaming (Avalon-ST) / Avalon memory-mapped (Avalon-MM) user-side interfaces
User packet interface with separate header, data and prefix
User packet interface can handle up to two TLPs in any given cycle (x16 mode only)
Up to 512 outstanding non-posted requests (x16 core only)
Up to 256 outstanding non-posted requests (x8 and x4 cores)
Supports autonomous Hard IP mode
- This mode allows the PCIe Hard IP to communicate with the Host before the FPGA configuration and entry into user mode are complete.
FPGA core configuration via PCIe link (CVP Init and CVP Update)

IP Debug Features:

Debug toolkit including the following features:
- Protocol and link status information
- Basic and advanced debugging capabilities including PMA register access and Eye viewing capability.

Driver Support:

Linux*/Windows* device drivers

Device Support

Table 1. Device Support and Number of Hardened PCI Express IP Blocks

Device Family	*Number of Hardened PCI Express IP Blocks**	PCI Express Link Speed
Device Family	*Number of Hardened PCI Express IP Blocks**	Gen1 (2.5 GT/s)	Gen2 (5.0 GT/s)	Gen3 (8.0 GT/s)	Gen4 (16.0 GT/s)	Gen5 (32.0 GT/s)
Intel® Agilex™	1 to 3 per device	✓	✓	✓	✓	✓
Intel® Stratix® 10	1 to 4 per device	✓	✓	✓	✓
Intel® Arria®10	1 to 4 per device	✓	✓	✓
Intel® Cyclone® 10	1 per device	✓	✓
Stratix® V	1 to 4 per device	✓	✓	✓
Arria® V	1 or 2 per device	✓	✓
Intel® Cyclone® 10 GX	1 per device	✓	✓
Cyclone® V GT	2 per device	✓	✓
Cyclone® V GX	1 or 2 per device	✓
Stratix® IV	2 to 4 per device	✓	✓
Cyclone® IV GX	1 per device	✓
Arria® II GZ	1 per device	✓	✓
Arria® II GX	1 per device	✓

Table 2. Device Configurations and Features Support

Interface Type		Avalon®-ST	Avalon-MM	Avalon-MM with DMA	SR-IOV	CvP / PRoP
Device/Configuration
Intel® Agilex™	Endpoint	Up to Gen4 x16	Up to Gen4 x16	Up to Gen4 x16	Available	Up to Gen4 x16: CvP Init
Intel® Agilex™	Root Port	Up to Gen4 x16	Up to Gen4 x16	-	-	-
Intel® Stratix® 10	Endpoint	Up to Gen4 x16	Up to Gen4 x16	Up to Gen4 x16	Available	Up to Gen4 x16: CvP Init
Intel® Stratix® 10	Root Port	Up to Gen4 x16	Up to Gen4 x16	-	-	-
Intel® Arria® 10	Endpoint	Up to Gen3 x8	Up to Gen3 x4	Gen1 x8, Gen2 x4, Gen2 x8, Gen3 x2, Gen3 x4, Gen3 x8	Available	Up to Gen3 x8: CvP and PRoP
Intel® Arria® 10	Root Port	Up to Gen3 x8	Up to Gen3 x4	-	-	-
Intel® Cyclone® 10 GX	Endpoint	Up to Gen2 x4	Up to Gen2 x4	Gen2 x4	-	Up to Gen2 x4: CvP and PRoP
Intel® Cyclone® 10 GX	Rootport	Up to Gen2 x4	Up to Gen2 x4	-	-	-
Stratix® V	Endpoint	Up to Gen3 x8	Up to Gen3 x4	Gen1 x8, Gen2 x4, Gen2 x8 Gen3 x2, Gen3 x4, Gen3 x8	Available	Gen1: CvP Init and CvP Update Gen2: CvP Init and CvP Update
Stratix® V	Root Port	Up to Gen3 x8	Up to Gen3 x4	-	-	-
Arria® V GZ	Endpoint	Up to Gen3 x8	Up to Gen3 x4	Gen1 x8, Gen2 x4, Gen2 x8 Gen3 x2, Gen3 x4, Gen3 x8	-	Gen1: CvP Init and CvP Update Gen2: CvP Init and CvP Update
Arria® V GZ	Root Port	Up to Gen3 x8	Up to Gen3 x4	-	-	-
Arria® V	Endpoint	Up to Gen1 x8 and Gen2 x4	Up to Gen1 x8 and Gen2 x4 (no x2)	Gen1 x8, Gen2 x4	-	Up to Gen1 x8 and Gen2 x4 Gen1: CvP Init and CvP Update Gen2: CvP Init
Arria® V	Root Port	Up to Gen1 x8 and Gen2 x4	Up to Gen1 x8 and Gen2 x4 (no x2)	-	-	-
Cyclone® V	Endpoint	Up to Gen2 x4	Up to Gen2 x4 (no x2)	Gen2 x4	-	Up to Gen2 x4 Gen1: CvP Init and CvP Update Gen2: CvP Init
Cyclone® V	Root Port	Up to Gen2 x4	Up to Gen2 x4 (no x2)	-	-	-

CvP – Configuration via Protocol
PRoP – Partial Reconfiguration over PCI Express
SR-IOV – Single Root I/O Virtualization
DMA – Direct Memory Access

IP Quality Metrics

Table 3. PCI Express IP Quality Metrics

Basics
Year IP was first released	2005
Latest version of Intel® Quartus^® Prime software supported	20.2
Status	Production
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Timing and/or layout constraints Documentation with revision control	Y for all, except for providing Readme files
Any additional customer deliverables provided with IP	Testbench and design examples
Parameterization GUI allowing end user to configure IP	Y
IP core is enabled for Intel® FPGA IP Evaluation Mode Support	Y
Source language	Verilog
Testbench language	Verilog
Software drivers provided	Y
Driver OS Support	Linux/Windows
Implementation
User interface	Avalon® Streaming, Avalon Memory-Mapped
IP-XACT metadata	N
Verification
Simulators supported	NCSim, ModelSim, VCS
Hardware validated	Intel® Arria® 10, Intel® Stratix® 10
Industry standard compliance testing performed	Y
If Yes, which test(s)?	PCI-SIG
If Yes, on which Intel FPGA device(s)?	Intel Stratix 10 GX L-Tile, Intel Stratix 10 GX H-tile, Intel Stratix 10 DX P-Tile
If Yes, date performed	Aug 2019 (Intel Stratix 10 FPGA P-Tile)
If No, is it planned?	N/A
Interoperability
IP has undergone interoperability testing	Y
If yes, on which Intel FPGA device(s)	Intel Stratix 10 GX L-Tile/H-Tile, Intel Stratix 10 DX P-Tile
Interoperability reports available	Y

Documentation

Intel offers a host of PCIe reference designs and application notes. These reference designs and application notes offer ready-made solutions that can be leveraged for feasibility studies, device selections, and design proofing on Intel^® FPGAs and SoCs.

The Intel FPGA development kits complement the reference designs and application notes by delivering a complete system-level design environment that includes both the hardware and software needed to immediately begin developing designs. Each reference design indicates which Intel® FPGA development kit and version of the Intel® Quartus^® software (version 15.1 and above) software were used for its development cycle.

As PCIe is a very configurable IP solution and supports numerous application needs, we cannot offer reference designs for every configuration or application possible. If there is no readily available reference design for your particular configuration or device, you may use a similar design and modify and/or port it as needed to fit your design requirements.

User guides and reference designs are available on the new PCI Express IP Support Center.

Technical Support

For technical support on this Intel^® FPGA IP function, please visit PCI Express-Support Center. You may also search for related topics on this function in the Knowledge Database.