PCI Express Core

from Northwest Logic, Inc.

Block Diagram

Block Diagram

Figure 1 shows the block diagram for the PCI Express megafunction.

Figure 1. Block Diagram for the PCI Express Megafunction

Block Diagram for the PCI Express Megafunction

View Full Size

The Expresso 3.0 Core is part of Northwest Logic's PCIe solution. This solution is designed to achieve maximum PCIe throughput while being easy to use.

The Expresso 3.0 Core separately, or in combination with the Northwest Logic DMA Core and DMA Driver, provides the maximum system throughput on a PCIe link. Contact Northwest Logic for more details.

The core is specifically designed for ease of use, including full release packet decoding, complete error handling, automatic handling of PCIe message packets, and comprehensive system debug and link monitoring support.

The core is delivered fully integrated and verified with the user's target PHY. Contact Northwest Logic for a complete list of supported PHYs. To accelerate simulations, the core is also delivered integrated with a fast simulating behavioral PHY.

The core is also provided with the Expresso Testbench which provides a PCIe Bus Functional Model.

The core is fully compliant with the current version of the PCI Express Base Specificaiton 3.0. The core includes all of the required 3.0 features including physical functions, SR-IOV, and flexible equalization support. To keep clock rates manageable, Northwest Logic also supplies a 256 bit side version of the core.

The core has been extensively validated with the Avery Logic PCI-Xactor PCI Express Compliance Suite and Northwest Logic Expresso Testbench.

Northwest Logic also provides intellectual property (IP) core customization services. Contact Northwest Logic for a quote.

  • High-performance, easy-to-use core
  • PCI Express® (PCIe®) Base Specification Revision 3.0 / 2.0 / 1.1 compliant
  • x1, x4, x8, and x16 lane support
  • 8.0, 5.0, and 2.5 Gbps serializer/deserializer (SERDES) support
  • 1 - 8 physical function support
  • SR-IOV support with up to 255 virtual functions
  • Endpoint, root port, upstream switch port, downstream switch port, and bifurcation support
  • 32, 64, 128, and 256 bit core width support
  • Transaction Layer Bypass option
  • AER, ECRC, MSI-X, Multivector MSI, Lane Reversal support
  • Delivered fully integrated and verified with target PCIe PHY
  • Provided with a PCIe testbench
  • Fully validated
  • Supports all Altera® FPGAs
  • Source code available
  • Customization and integration services available

Contact Northwest Logic

  • Core (netlist or source code)
  • Comprehensive verification suite (source code)
  • Complete documentation
  • Expert technical support and maintenance updates

For additional information, contact Northwest Logic, Inc. at:

Northwest Logic, Inc.
1100 NW Compton Drive, Ste. 100
Beaverton, OR 97006
Tel: (503) 533-5800 x309
Fax: (503) 533-5900
Email: info@nwlogic.com
Website: www.nwlogic.com