Integrated PCI Core

from Northwest Logic, Inc.

Block Diagram

Block Diagram

Figure 1 shows a block diagram of the function.

Figure 1. Integrated PCI Core Block Diagram

Figure 1. Integrated PCI Core Block Diagram

View Full Size

Northwest Logic's integrated PCI core is specifically designed to enable you to implement a high-performance PCI system with no additional PCI logic design. The integrated PCI core accomplishes this by integrating Northwest Logic's PCI core with a high-performance back-end module.

The integrated PCI core enables the maximum possible PCI throughput to be achieved through the use of independent FIFO interfaces: master write, target write, master read, and target read. The FIFO interfaces support multiple posted writes, delayed reads, and read pre-fetching operations. In addition, the FIFO interfaces enable PCI bus and local bus data transfers to occur simultaneously.

The core fully complies with all PCI transaction and ordering rules in accordance with the PCI specification.

The core is available in several versions including 32 or 32/64 bit, target-only or master/target, and peripheral or host.

The integrated PCI core is provided with Northwest Logic's PCI-X/PCI Verification Suite with complete scripting and random stimulus capabilities, enabling your design to be fully validated prior to use in hardware.

Northwest Logic also provides customization and integration services to produce complete logic designs.

  • Pre-integrated—requires minimal PCI expertise and design effort to use
  • Provides maximum PCI throughput by supporting multiple posted writes, delayed reads, and read pre-fetching
  • Fully compliant with PCI transaction and ordering rules
  • Independent first-in first-out (FIFO) interfaces enable simultaneous PCI and local bus data transfers
  • Optional read streaming mode supports applications requiring high read data throughput
  • User-expandable configuration space can be loaded from EEPROM
  • 33/66 MHz or 32/64-bit, host or peripheral, master/target, or target-only versions available
  • Provided with the Northwest Logic PCI-X/PCI Verification Suite (in source)
  • Core available in source code
  • Customization and integration services available
  • PCI Local Bus Specification Revision 3.0 compliant
  • Fast response, expert technical support provided by Northwest Logic IP designers

Table 1 lists the typical device utilization results for the megafunction.

Table 1. Typical Device Utilization for the Megafunction

Supported Altera® Devices Speed Grade Utilization
Logic Elements
Performance
(fMAX)
Parameter Settings
Stratix® II,
Stratix II GX
-51,300
32-bit target only
1,700
64-bit target only
2,700
64-bit master/target
66 MHzContact Northwest Logic
Stratix,
Stratix GX
-61,300
32-bit target only
1,700
64-bit target only
2,700
64-bit master/target
66 MHzContact Northwest Logic
Cyclone® II-71,300
32-bit target only
1,700
64-bit target only
2,700
64-bit master/target
66 MHz Contact Northwest Logic

Cyclone-71,300
32-bit target only
1,700
64-bit target only
2,700
64-bit master/target
66 MHzContact Northwest Logic
  • Core (netlist or source code)
  • Comprehensive Verification Suite (source code)
  • Complete documentation
  • Expert technical support and maintenance updates

For additional information, contact Northwest Logic at:

Northwest Logic, Inc.
1100 NW Compton Drive, Ste. 100
Beaverton, OR 97006
Tel: (503) 533-5800 x309
Fax: (503) 533-5900
Email: info@nwlogic.com
Website: www.nwlogic.com