Nios II Advanced CAN

from IFI

Block Diagram

Figure 1 shows a block diagram of the function.

Figure1. Advanced-Can Block Diagram

Figure 1 Advanced-Can Block DiagramView full detail (180 KB)

  • Small but efficient CAN controller
  • Easily integrated into Nios II systems using SOPC Builder
  • Avalon® interface for Nios II processor
  • Royalty free
  • Software drivers shipped with intellectual property (IP)
  • Verified on Nios II development board
  • Evaluation version available
  • Software examples included

The Nios® II Advanced CAN bus core includes the following features:

  • CAN 2.0B
  • Up to 256 message transmit buffer
  • Up to 256 message receive buffer
  • Up to 256 message filters
  • Nios II embedded processor interface
  • Silent mode
  • High priority messages
  • Time stamp

Table 1 lists the typical device utilization results for the megafunction.

Table 1. Typical Device Utilization
Target Device

Utilization Logic
Elements (LEs) (1)

M4K Memory Blocks I/O Pins
Cyclone FPGA 1350 3-24 3
Cyclone II FPGA 1350 3-24 3
Cyclone III FPGA 1350 3-24 3
Stratix FPGA 1350 3-24 3
Stratix II FPGA 1350 3-24 3
Stratix III FPGA 1350 3-24 3
  1. The Quartus® II software reports the number of adaptive look-up tables (ALUTs) that the design uses in Stratix II devices. The LE count is based on this number of ALUTs.

For additional information, contact:

Ingenieurbüro Für IC-Technologie
Kleiner Weg 3
97877 Wertheim
Tel: +49/9342/96080
Fax: +49/9342/5381