Gigabit Ethernet MAC Controller Physical Coding Sublayer (MAC 1G PCS)

from CAST, Inc.

Features

Figure 1. CCIR-656 Decoder Function
  • Based on the Intel/DEC 21143 LAN controller
  • Support for 10- and 100-Mbps data transfer rates
  • Media independent interface (MII)
  • Compliant with IEEE 802.3 carrier sense multiple access with collision detection (CSMA/CD) standard
  • Full or half duplex operation
  • Flexible address filtering
  • External RAM for storing media access control (MAC) addresses
  • Up to 16 physical addresses
  • 512-bit hash table for multicast addresses
  • Configurable 8-, 16-, and 32-bit data bus length
  • Big or little endian data byte ordering
  • Rich set of control and status registers
  • Interrupt mitigation control mechanism
  • Direct memory access (DMA) controller for programmable burst length
  • DMA controller for intelligent arbitration between transmit and receive processes
  • Descriptor "ring" or "chain" structures
  • Single descriptor points to up to two data buffers
  • Automatic descriptor list pooling

Block Diagram

Figure 1 shows a block diagram of the function.

Figure 1. MAC Ethernet Controller Block Diagram

Figure 1. CCIR-656 Decoder Function
Click for full detail (57KB)

Description

The MAC Ethernet controller is a megafunction of a high-speed local-area network (LAN) controller. It implements CSMA/CD algorithms as defined by the IEEE 802.3 standard for MAC over the Ethernet.

This megafunction is based on the standard Intel/DEC 21143 chip and contains a register set and functionality similar to the original device. It also contains a generic host side interface for connecting with external CPUs or with standard bus controllers such as PCI. The host interface is compatible with most modern virtual component interfaces, and can be configured to work with either 8-, 16-, or 32-bit data bus lengths with big or little endian byte ordering.

Developed for reuse in FPGA and ASIC implementations, the MAC Ethernet controller has a strictly synchronous design with positive-edge clocking, no internal tri-states, and a synchronous reset.

Device Utilization & Performance

Table 1 lists the typical device utilization results for the megafunction.

Table 1. Typical Device Utilization for the Megafunction

Target Device Speed Grade Utilization Performance
fmax
Logic Elements (LEs) Embedded array blocks (EABs)I/O Pins
EP1K100-14,074920072 MHz
EP20K200C-74,0821720085 MHz
EP2A15-74,084920099 MHz
EP1S10-63,6019200129 MHz

Deliverables

  • EDIF netlist
  • Assignment & configuration
  • Symbol file
  • Include file
  • Vectors for testing the functionality of the megafunction including expected results
  • Documentation

Contact Information

For additional information, contact:

CAST, Inc.
11 Stonewall Court
Woodcliff Lake, NJ 07677

Tel: (201) 391-8300
Fax: (201) 391-8694
E-mail: info@cast-inc.com
WWW: WWW: http://www.cast-inc.com