The MAC Ethernet controller is a megafunction of a high-speed local-area network (LAN) controller. It implements CSMA/CD algorithms as defined by the IEEE 802.3 standard for MAC over the Ethernet.
This megafunction is based on the standard Intel/DEC 21143 chip and contains a register set and functionality similar to the original device. It also contains a generic host side interface for connecting with external CPUs or with standard bus controllers such as PCI. The host interface is compatible with most modern virtual component interfaces, and can be configured to work with either 8-, 16-, or 32-bit data bus lengths with big or little endian byte ordering.
Developed for reuse in FPGA and ASIC implementations, the MAC Ethernet controller has a strictly synchronous design with positive-edge clocking, no internal tri-states, and a synchronous reset.
Device Utilization & Performance
Table 1 lists the typical device utilization results for the megafunction.
Table 1. Typical Device Utilization for the Megafunction
Logic Elements (LEs)
Embedded array blocks (EABs)
Assignment & configuration
Vectors for testing the functionality of the megafunction including expected results
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