Serial Lite IV Intel® FPGA IP Core

Serial Lite IV High Level Block Diagram

Serial Lite IV Intel® FPGA intellectual property (IP) core is suitable for high-bandwidth data communication for chip-to-chip, board-to-board, and backplane applications.

 

Serial Lite IV IP core incorporates a media access control (MAC), physical coding sublayer (PCS), and physical media attachment (PMA) block. The IP supports data transfer up to 56 Gbps per lane with a maximum of eight PAM4 lanes in a single link or 28 Gbps per lane with a maximum of 16 non-return-to-zero (NRZ) lanes. This protocol offers high bandwidth, low overhead frames, low I/O count, and supports high scalability in both numbers of lanes and speed. The IP is easily reconfigurable with support of a wide range of data rates with Ethernet PCS mode of the E-tile transceiver.

 

This IP supports two transmission modes:

  • Basic mode—This is a pure streaming mode where data is sent without the start-of-packet, empty cycle, and end-of-packet to increase bandwidth. The IP takes the first valid data as the start of a burst.
  • Full mode—This is the packet mode of data transfer. A burst and sync cycle is sent at the start and at the end of a packet as delimiters.

Serial Lite IV Intel® FPGA IP Features

Feature Description

Data Transfer

  • Supports up to 56 Gbps per lane with a maximum of eight PAM4 lanes in a single link.
  • Supports up to 28 Gbps per with a maximum of 16 NRZ lanes.
  • Supports continuous streaming (Basic) or packet (Full) modes.
  • Supports low overhead frame packets.
  • pports byte granularity transfer for every burst size.
  • Supports user-initiated or automatic lane alignment.
  • Supports programmable alignment period.

PCS

  • Uses hard IP logic that interfaces seamlessly to Intel® Agilex™ and Intel Stratix® 10 device E-tile transceivers for soft logic resource reduction.
  • Supports PAM4 modulation mode for 100GBASE-KP4 specification. RS-FEC is always enabled in this modulation mode.
  • Supports NRZ modulation mode with KR-FEC error detection and correction.
  • Supports 64b/66b encoding decoding.

Error Detection and Handling

  • Supports cyckic redundancy check (CRC) error checking on transmit (TX) and receive (RX) datapaths.
  • Supports RX link error checking.
  • Supports RX PCS error detection.

Interfaces

  • Supports only full duplex packet transfer with independent links.
  • Uses point-to-point interconnect to multiple FPGAs with low transfer latency.
  • Supports user-defined commands.

The Serial Lite IV Streaming Intel® FPGA IP core is supported on the following device families:

Serial Lite IV IP Quality Metrics

Basics

Year IP was first released

2019

Latest version of the Intel® Quartus® Prime Design Software supported

19.3

Status

Advanced

Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)

  • Simulation model for ModelSim*- Intel FPGA Edition
  • Timing and/or layout constraints

  • Documentation with revision control

Y for all

Any additional customer deliverables provided with IP

Testbench and design examples

Parameterization GUI allowing end user to configure IP

Y

IP is enabled for Intel FPGA IP Evaluation Mode Support

Y

Source language

Verilog 

Testbench language

Verilog

Software drivers provided

N

Driver OS Support

N

Implementation

User interface

Avalon® Streaming

IP-XACT metadata

N

Verification

Simulators supported

NCSim, ModelSim*, VCS/VCSMX

Hardware validated

Intel Agilex® FPGA Development Kit, Intel Stratix® 10 FPGA Signal Integrity Development Kit

Industry-standard compliance testing performed

N

If Yes, which test(s)?

N/A

If Yes, on which Intel FPGA device(s)?

N/A

If Yes, date performed

N/A

If No, is it planned?

N

Interoperability

IP has undergone interoperability testing

N/A

If yes, on which Intel FPGA device(s)

N/A

Interoperability reports available

N/A

For technical support on this IP core, please visit Intel® Premier Support. You may also search for related topics on this function in the Knowledge Center.

† Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit www.intel.com/benchmarks.

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