SerialLite II Intel® FPGA IP Core

Figure 1. Typical Application Block Diagram

The SerialLite II Intel® FPGA IP core provides a simple and lightweight way to move data from one point to another reliably at high speeds. It consists of a serial link of up to 16 bonded lanes with logic to provide a number of basic and optional link support functions. The Atlantic* interface is the primary access for delivering and receiving data.

The SerialLite II protocol specifies a link that is simple to build, uses as little logic as possible, and requires little work to implement. The SerialLite II IP is feature-rich, and can be parameterized through a powerful graphical user interface (GUI).

A link built using the SerialLite II Intel FPGA IP core can operate from 622 Mbps to 6.375 Gbps per lane. Intel Arria® 10 devices using the IP core can operate well above 6.375 Gbps per lane. Link reliability is enhanced by the 8B/10B encoding scheme and optional cyclic redundancy check (CRC) capabilities. Further reductions in the bit-error rate can be achieved using the optional retry-on-error feature. Data rate and consumption mismatches can be accommodated using the optional flow-control feature to ensure that no data is lost.

Note that the Intel Arria 10 and Cyclone® V device families indirectly support the use of the SerialLite II Intel FPGA IP core in the Intel Quartus® design software. If your design requires the IP core on Intel Arria 10 or Cyclone V devices, please contact your local sales representative for a special license and easy-to-follow implementation guidelines.

  • Physical layer features
    • 622 Mbps to 6.375 Gbps per lane (< data rate support for Arria 10 devices)
    • Single or multiple lane support (up to 16 lanes)
    • 8 bit, 16 bit, or 32 bit datapath per lane
    • Symmetric, asymmetric, unidirectional/simplex, or broadcast mode
    • Optional payload and idle scrambling / de-scrambling
    • Self-synchronizing link state machine
    • Channel bonding scalable up to 16 lanes
    • Synchronous or asynchronous operation
      • Automatic clock rate compensation for asynchronous use
      • +/-100 and +/-300 parts per million (ppm)
  • Link layer features
    • Atlantic interface compliant
    • Support for two types of user packets: data packet and priority packet
    • Optional packet integrity protection support using CRC-32 or CRC-16
    • Optional retry-on-error for priority packets
    • Individual port (data/priority) flow control
    • Unrestricted data and priority packet size
    • Optional link management packets
  • Full support of asymmetrical, unidirectional, and broadcast modes at rates up to 3.125 Gbps (please refer to user guide)
  • Easy-to-use GUI interface
  • IP functional simulation models for use in Intel FPGA-supported VHDL and Verilog HDL simulators

The SerialLite II Intel FPGA IP core is supported on the following device families:

For technical support on this IP core, please visit Intel Premier Support. You may also search for related topics on this function in the Knowledge Base.