SDI II Intel® FPGA IP Core

SDI IP Diagram in V Series
12G SDI Diagram in 10 Series

The serial digital interface (SDI) II intellectual property (IP) core implements a transmitter, receiver or full-duplex SDI at standard definition, high definition or 3G to 12G rate as defined by the Society of Motion Picture and Television Engineers. The SDI II IP core supports multiple standards. These modes provide automatic receiver rate detection and transceiver dynamic reconfiguration.

The SDI II IP core highlights the following new features:

  • IEEE encryption for functional simulation across a variety of tools
  • Dynamic generation of user simulation testbench that matches the IP configuration
  • Dynamic generation of design example that serves as common entity for simulation and hardware verification

IP Core Feature

Description

Transceiver data interface

20 bit and 80 bit

Supported SDI standards and video formats

  • Single Standard
    • Standard Definition or SD-SDI
    • High Definition or HD-SDI
    • 3 gigabits per second (Gbps) or 3G-SDI
    • Dual Link HD-SDI
  • Multiple Standards
    • Dual Standard up to HD-SDI
    • Triple Standard up to 3G-SDI
    • Multi Standard up to 12G-SDI

Note: Not all devices support all formats, see “Device Support” below

SMPTE support

  • SMPTE425M level A support (direct source image formatting)
  • SMPTE425M level B support (dual link mapping)

Other features

  • Payload identification packet insertion and extraction
  • Clock enable generator
  • Video rate detection
  • Cyclic redundancy check (CRC) encoding and decoding (except SD)
  • Dual link data stream synchronization (only HD)
  Single Standard
Multiple Standards
Device Family
SD-SDI HD-SDI
3G-SDI

Dual Link

HD-SDI

Dual Standard

(up to HD)

Triple Standard

(up to 3G)

Multi Standard

(up to 12G)

Intel® Stratix® 10 No Yes Yes Yes No Yes Yes
Intel Arria® 10 No Yes Yes Yes No Yes Yes
Intel Cyclone® 10
No Yes Yes Yes No Yes Yes
Stratix V Yes Yes Yes Yes Yes Yes No
Arria V GX Yes Yes Yes Yes Yes Yes No
Arria V GZ
Yes Yes Yes Yes Yes Yes No
Cyclone V
Yes Yes Yes Yes Yes Yes No

For previous generation device support, visit the Serial Digital Interface IP Core Resource Center.

Basics

Year IP was first released

2006

Latest version of Intel® Quartus® Prime design software supported

18.0

Status

Production

Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim*- Intel FPGA Edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file

  • Yes
  • Yes
  • Yes
  • Yes
  • Yes
  • No

Any additional customer deliverables provided with IP

None

Parameterization GUI allowing end user to configure IP

Yes

IP core is enabled for the Intel FPGA IP Evaluation Mode Support

Yes

Source language

Both Verilog and VHDL

Testbench language

Both Verilog and VHDL

Software drivers provided

No

Driver operating system (OS) support

N/A

Implementation

User interface

Other (Parallel Video)

IP-XACT metadata

No

Verification

Simulators supported

ModelSim, VCS, Riviera-PRO, NCSim

Hardware validated

Intel Arria® 10, Intel Cyclone® 10, Arria V GX/GZ, Cyclone V, Stratix V

Industry standard compliance testing performed

No

If Yes, which test(s)?

N/A

If Yes, on which Intel FPGA device(s)?

N/A

If Yes, date performed

N/A

If No, is it planned?

No

Interoperability

IP has undergone interoperability testing

Yes

If yes, on which Intel FPGA device(s)

Intel Stratix® 10, Intel Arria 10, Intel Cyclone 10, Stratix V, Arria V, Cyclone V

Interoperability reports available

Contact Sales

Design Examples and Development Kits

The following design examples are available for you to run on our development kits.

Video Tutorials

The following video tutorials are available for you to learn about using this IP.

Videos Description

SDI II IP Step-by -Step Implementation Guide for an Intel Arria 10 Device (8 min)

This video demonstrates how to implement an SDI II IP core in an Intel Arria 10 device. You will be guided through step by step generation in Intel Quartus software for all necessary transceiver-related components and integration.

SDI II Dynamic TX Clock Switching Feature Implementation and Hardware Verification (4 min)

This video provides theory of operation and a demonstration of the implementation of the SDI II dynamic TX clock switching capability for Intel Arria 10 devices.

Additional support for these Intel FPGA IP cores is available from Intel Premier Support.