RapidIO Intel® FPGA IP

Intel is discontinuing the intellectual property (IP) for RapidIO I and RapidIO II, more information can be found in the product discontinuance notification (PDN2025). 

RapidIO High-Speed Interconnect

 

Intel Offers Two Distinct Intel® FPGA IPs for RapidIO:

  • RapidIO II Intel FPGA IP complies with the RapidIO Specification Revision 2.2
    • Physical, transport, and logical layer separations (modular architecture)
    • IDLE2 sequence - long control symbol
    • 1.25, 2.5, 3.125, 5.0 and 6.25 Gbaud lane rates with 1X, 2X, and 4X link widths
  • RapidIO Intel FPGA IP complies with the RapidIO Specification Revisions 1.3 / 2.1
    • Physical, transport, and logical layer separations (modular architecture)
    • IDLE1 sequence - short control symbol
    • 1.25, 2.5, 3.125, and 5.0 Gbaud lane rates with 1X and 4X link widths

For device support details, such as lane rates, link widths, and speed grades, refer to the RapidIO Intel FPGA IP user guides.

Features

 
A significant portion of the wireless industry adopts the RapidIO* standard as a high-speed interconnect. The RapidIO standard is typically used between digital signal processors as well as between the Control Plane Processors and memory. RapidIO is also gaining acceptance as a backplane interconnect due to its adoption of widely used standards for the electrical characteristics of the physical media attachment (PMA), such as XAUI or CEI for up to 6.25 Gbaud data rate. Intel® FPGAs are also capable of supporting RapidIO Gen3 data rates.
  • PHY based on embedded transceivers
  • Easy to use
    • Intellectual property (IP) parameter editor allows easy manual optimization of parameters, such as interface FIFO depths, address translation windows, output differential voltage, and pre-emphasis
    • Easy configuration provides ways to reduce resource utilization to create smaller Intel® FPGA IP function variations depending on application needs
    • Platform Designer for system interconnect
  • Robust solution
    • Endpoint IP core, testbenches with proven interoperability with leading digital signal processor and switch vendors
    • Compliant to RapidIO* specification, Revision 1.3 / 2.1 and 2.2

For a system-level integration-ready solution, you can save several months of design time by selecting all RapidIO layers—including features, such as address translation as well as simple Avalon® Memory-Mapped (Avalon-MM) and Avalon Streaming (Avalon-ST) FIFO interfaces.

Protocol Solution

Figure 1 shows an example of a system built using the Platform Designer with a Nios® II soft embedded processor as a processing element. The program memory can include “boot code” for system-level enumeration of the various endpoints. The program also configures the capability address registers of the endpoints and the Intel FPGA IP function.

Figure 1. A Complete SRIO System

IP Quality Metrics

Basics

Year IP was first released

2009

Latest version of Intel® Quartus® Prime software supported

18.1

Status

Production

Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim*- Intel® FPGA Edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file

  • Yes
  • Yes
  • Yes
  • Yes
  • Yes
  • No

Any additional customer deliverables provided with IP

None

Parameterization GUI allowing end user to configure IP

Yes

IP core is enabled for Intel FPGA IP Evaluation Mode Support

Yes

Source language

Both Verilog and VHDL

Testbench language

Both Verilog and VHDL

Software drivers provided

No

Driver operating system (OS) support

N/A

Implementation

User interface

Avalon®-MM, Avalon-ST

IP-XACT metadata

No

Verification

Simulators supported

ModelSim*, VCS, Riviera-PRO, NCSim

Hardware validated

Intel® Arria® 10, Arria V, Intel® Cyclone® 10 GX, Cyclone V, Intel® Stratix® 10, Stratix V

Industry-standard compliance testing performed

No

If Yes, which test(s)?

N/A

If Yes, on which Intel FPGA device(s)?

N/A

If Yes, date performed

N/A

If No, is it planned?

No

Interoperability

IP has undergone interoperability testing

Yes

If yes, on which Intel FPGA device(s)

Arria V, Intel Arria 10, Intel Cyclone 10 GX, Intel Stratix 10

Interoperability reports available

Yes

Documentation

 

User Guides

Reference Designs

Intel FPGA IP Evaluation Mode 

Find the IP you need for Intel FPGAs, SoCs, and Structured ASICs

For a complete list of Intel and third-party IPs, please visit the Find IP page. 

Related Links

 

For technical support on this IP core, please visit Intel® Premier Support. You may also search for related topics on this function in the Knowledge Center.

 

† Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase.  For more complete information about performance and benchmark results, visit www.intel.com/benchmarks.Intel and Quartus are trademarks of Intel Corporation or its subsidiaries in the US and/or other countries.