Interlaken Intel® FPGA IP

Interlaken Interconnect Protocol

Interlaken is an interconnect protocol for high-speed, channelized chip-to-chip interface in networking applications. It is optimized for high-bandwidth chip-to-chip packet transfers at rates from 10 Gbps to 300 Gbps and beyond. The Interlaken IP core is Interlaken Protocol Definition v1.2 compliant and allows system developers to achieve high bandwidth throughput in their systems. This pre-built, ready-to-go IP building block shortens the design cycle resulting in faster time to market.

Intel FPGA Interlaken IP core is ideal for:

Multi-terabit routers and switches for access
Carrier Ethernet and data center applications that demand IP configurability to optimize for various traffic profiles
Scalability for next-generation platforms

Contact Intel Sales User Guides IP Evaluation and Purchase

Features

Intel has been a part of the Interlaken Alliance since its inception in 2007 and continues to innovate new protocol features to provide customers with robust and easy-to-implement Interlaken IP solutions. Intel now offers up to 300G Interlaken IP.

With the release of Intel's next-generation Intel® Arria® 10 FPGAs and SoCs, the Intel FPGA Interlaken IP Portfolio accomplishes major development milestones: third-generation soft IP (includes media access control (MAC) and second-generation hardened IP (includes physical coding sublayer (PCS) / physical medium attachment (PMA). These seasoned, battle-tested cores continue to provide the additional robustness and maturity required for new, more intelligent systems.

Data rate selection up to 25.78125 Gbps (NRZ) OR 56 Gbps (PAM4)
Multi-lane configuration up to 24 lanes
Interleave packet mode support
Enhanced scheduling
Multi-segment or Start-of-Packet (SOP) alignment user interface options
I/O controllable burst settings (Min, Max, Short)
Programmable meta frame lengths
Up to 256 logical channels
Multiple-use field access
In-band and out-of-band flow control (calendar page options)
Advanced error handling and error injection capabilities
Retransmission
Fully integrated IP (MAC, PCS, and PMA layers)
Tunable pre-emphasis and equalization settings
Custom IP deliveries available to optimize for various application needs

Device Support

IP Quality Metrics

Basics
Year IP was first released	2012
Latest version of Intel® Quartus® Prime software supported	20.2
Status	Production
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim*- Intel® FPGA Edition Timing and/or layout constraints Documentation with revision control	Y for all
Any additional customer deliverables provided with IP	Testbench and design examples
Parameterization GUI allowing end user to configure IP	N
IP is enabled for the Intel FPGA IP Evaluation Mode Support	Y
Source language	Verilog
Testbench language	Verilog
Software drivers provided	N
Driver operating system (OS) support	N/A
Implementation
User interface	Avalon® ST-like
IP-XACT metadata	N
Verification
Simulators supported	NCSim, ModelSim, VCS/VCSMX, Xcelium
Hardware validated	Intel® Arria® 10 FPGA Transceiver Signal Integrity Development Kit, Intel® Stratix® 10 FPGA Signal Integrity Development Kit Intel® Agilex™ F-series Transceiver SoC Development Kit
Industry-standard compliance testing performed	N/A
If Yes, which test(s)?	N/A
If Yes, on which Intel FPGA device(s)?	N/A
If Yes, date performed	N/A
If No, is it planned?	N
Interoperability
IP has undergone interoperability testing	N
If yes, on which Intel FPGA device(s)
Interoperability reports available	N