Interlaken is a scalable protocol that enables chip-to-chip packet transfers at rates from 10 Gbps to 300 Gbps and beyond. The Interlaken Intel® FPGA intellectual property (IP) core continues to scale with today’s demand for more bandwidth and higher performance needs. Intel has been a part of the Interlaken Alliance since its inception in 2007 and continues to innovate new protocol features to provide customers with robust and easy-to-implement Interlaken IP solutions. Intel entered the market with 10G Interlaken IP and now offers up to 300G Interlaken IP.
Table 1. Performance and Productivity You Can Expect
Parameter tuning enables maximal bandwidth realization for a given core configuration†
Adequate IP timing margin shortens full design timing closure†
Consistent delivery of high packet throughput on multiple customer platforms and across various vertical markets**†
Intel FPGA IP Evaluation Mode feature allows you to test drive IP for free and without a license
Unique combination of hard IP and soft IP modules delivers high design clock frequency performance†
Fully integrated Interlaken IP includes MAC, PCS, and PMA layers for easy FPGA IP integration
**Interlaken configuration specific
† Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit www.intel.com/benchmarks.