Interlaken Intel® FPGA IP Core
Automated Generation of SignalTap II Files for Arria® 10 IP Core Debug
Push-button Hardware Design Examples in Intel Quartus® Prime Software
Interlaken is a scalable protocol that enables chip-to-chip packet transfers at rates from 10 Gbps to 300 Gbps and beyond. The Interlaken Intel® FPGA intellectual property (IP) core continues to scale with today’s demand for more bandwidth and higher performance needs. Intel has been a part of the Interlaken Alliance since its inception in 2007 and continues to innovate new protocol features to provide customers with robust and easy-to-implement Interlaken IP solutions. Intel entered the market with 10G Interlaken IP and now offers up to 300G Interlaken IP.
Table 1. Performance and Productivity You Can Expect
| Performance | Productivity |
|---|---|
| Parameter tuning enables maximal bandwidth realization for a given core configuration† | Adequate IP timing margin shortens full design timing closure† |
| Consistent delivery of high packet throughput on multiple customer platforms and across various vertical markets**† | Intel FPGA IP Evaluation Mode feature allows you to test drive IP for free and without a license |
| Unique combination of hard IP and soft IP modules delivers high design clock frequency performance† | Fully integrated Interlaken IP includes MAC, PCS, and PMA layers for easy FPGA IP integration |
**Interlaken configuration specific
† Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit www.intel.com/benchmarks.
- Data rate selection up to 25 Gbps
- Multi-lane configuration up to 24 lanes
- Interleave (segment) mode and packet mode support
- Enhanced scheduling
- Multi-segment or Start-of-Packet (SOP) alignment user interface options
- I/O controllable burst settings (Min, Max, Short)
- Programmable meta frame lengths
- Up to 256 logical channels
- Multiple-use field access
- In-band and out-of-band flow control (calendar page options)
- Advanced error handling and error injection capabilities
- Retransmission
- Fully integrated IP (MAC, PCS, and PMA layers)
- Tunable pre-emphasis and equalization settings
- Custom IP deliveries available to optimize for various application needs
Table 2. Interlaken IP Quality Metrics
Basics |
|
|---|---|
Year IP was first released |
2012 |
Latest version of Intel® Quartus® Prime Design Software supported |
18.1 |
Status |
Production |
Deliverables |
|
Customer deliverables include the following:
|
Y for all, except for providing Readme file and support for ModelSim*- Intel FPGA Edition |
Any additional customer deliverables provided with IP |
Testbench and design examples |
Parameterization GUI allowing end user to configure IP |
Y |
IP is enabled for the Intel FPGA IP Evaluation Mode Support |
Y |
Source language |
Verilog and VHDL |
Testbench language |
Verilog |
Software drivers provided |
N |
Driver operating system (OS) support |
N/A |
Implementation |
|
User interface |
Avalon® Memory-Mapped |
IP-XACT metadata |
N |
Verification |
|
Simulators supported |
NCSim, ModelSim, VCS/VCSMX |
Hardware validated |
Arria® 10 Transceiver Signal Integrity Development Kit, Stratix® 10 Signal Integrity Development Kit |
Industry-standard compliance testing performed |
N/A |
If Yes, which test(s)? |
N/A |
If Yes, on which Intel FPGA device(s)? |
N/A |
If Yes, date performed |
N/A |
If No, is it planned? |
N |
Interoperability |
|
IP has undergone interoperability testing |
Y |
If yes, on which Intel FPGA device(s) |
Stratix V |
Interoperability reports available |
Y, Broadcom* ARAD and Cavium OCTEON* II |
For technical support on this IP, please visit Intel® Premier Support. You may also search for related topics on this function in the Knowledge Center.