Interlaken Intel® FPGA IP Core

Figure 1. Typical Application Block Diagram

Push-button Hardware Design Examples in Intel® Quartus® Prime Software

Interlaken is a scalable protocol that enables chip-to-chip packet transfers at rates from 10 Gbps to 300 Gbps and beyond. The Interlaken Intel® FPGA intellectual property (IP) core continues to scale with today’s demand for more bandwidth and higher performance needs. Intel has been a part of the Interlaken Alliance since its inception in 2007 and continues to innovate new protocol features to provide customers with robust and easy-to-implement Interlaken IP solutions. Intel entered the market with 10G Interlaken IP and now offers up to 300G Interlaken IP.

Table 1. Performance and Productivity You Can Expect

Performance Productivity
Parameter tuning enables maximal bandwidth realization for a given core configuration Adequate IP timing margin shortens full design timing closure
Consistent delivery of high packet throughput on multiple customer platforms and across various vertical markets** Intel FPGA IP Evaluation Mode feature allows you to test drive IP for free and without a license
Unique combination of hard IP and soft IP modules delivers high design clock frequency performance Fully integrated Interlaken IP includes MAC, PCS, and PMA layers for easy FPGA IP integration

**Interlaken configuration specific

† Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit

  • Data rate selection up to 25.78125 Gbps (NRZ) OR 56 Gbps (PAM4)
  • Multi-lane configuration up to 24 lanes
  • Interleave packet mode  support
  • Enhanced scheduling
  • Multi-segment or Start-of-Packet (SOP) alignment user interface options
  • I/O controllable burst settings (Min, Max, Short) 
  • Programmable meta frame lengths
  • Up to 256 logical channels
  • Multiple-use field access
  • In-band and out-of-band flow control (calendar page options)
  • Advanced error handling and error injection capabilities
  • Retransmission
  • Fully integrated IP (MAC, PCS, and PMA layers)
  • Tunable pre-emphasis and equalization settings
  • Custom IP deliveries available to optimize for various application needs

Table 2. Interlaken IP Quality Metrics


Year IP was first released


Latest version of Intel® Quartus® Prime software supported





Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim*- Intel® FPGA Edition
  • Timing and/or layout constraints
  • Documentation with revision control
Y for all

Any additional customer deliverables provided with IP

Testbench and design examples

Parameterization GUI allowing end user to configure IP


IP is enabled for the Intel FPGA IP Evaluation Mode Support


Source language


Testbench language


Software drivers provided


Driver operating system (OS) support



User interface

Avalon® ST-like

IP-XACT metadata



Simulators supported

NCSim, ModelSim, VCS/VCSMX, Xcelium

Hardware validated

Intel® Arria® 10  FPGA Transceiver Signal Integrity Development Kit,

Intel® Stratix® 10 FPGA Signal Integrity Development Kit

Intel® Agilex™ F-series Transceiver SoC Development Kit

Industry-standard compliance testing performed


If Yes, which test(s)?


If Yes, on which Intel FPGA device(s)?


If Yes, date performed


If No, is it planned?



IP has undergone interoperability testing


If yes, on which Intel FPGA device(s)


Interoperability reports available


For technical support on this IP, please visit Intel® Premier Support. You may also search for related topics on this function in the Knowledge Center.