50G Ethernet Intel® FPGA IP

The Intel®  50 Gbps Ethernet (50GbE) IP core implements the 25G & 50G Ethernet Specification, Draft 1.4 from the 25 Gigabit Ethernet Consortium and the IEEE 802.3by 25Gb Ethernet draft. The IP core includes an option to support unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012 Ethernet Standard. The MAC client side interface for the 50 Gbps Ethernet IP core is a 128-bit Avalon® Streaming (Avalon-ST) interface. It maps to two 25.78125 Gbps transceivers.

The IP core provides standard media access control (MAC) and physical coding sublayer (PCS), and PMA functions shown in the following block diagram. The PHY comprises the PCS and PMA.

PHY features:

  •  Soft PCS logic that interfaces seamlessly to Intel® Arria® 10 FPGA 25.78125 gigabits per second (Gbps) serial transceivers.

Frame structure control features:

  • Support for jumbo packets, defined as packets greater than 1,500 bytes.
  • Receive (RX) cyclic redundancy check (CRC) removal and pass-through control.Transmit (TX) CRC generation.
  • RX and TX preamble pass-through option for applications that requireproprietary user management information transfer.
  • TX automatic frame padding to meet the 64-byte minimum Ethernet frame length.

Frame monitoring and statistics:

  •  RX CRC checking and error reporting.
  •  Optional RX strict SFD checking per IEEE specification.
  • RX malformed packet checking per IEEE specification.
  • Optional fault signaling detects and reports local fault and generates remote
    fault, with IEEE 802.3ba-2012 Ethernet Standard Clause 66 support.
  • Unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012
    Ethernet Standard.

 Debug and testability features:

  • Programmable serial PMA local loopback (TX to RX) at the serial transceiver
    for self-diagnostic testing.
  •  Optional access to Altera Debug Master Endpoint (ADME) for serial link
    debugging or monitoring PHY signal integrity.

User system interfaces:

  • Avalon® Memory-Mapped (Avalon-MM) management interface to access the IP
    core control and status registers.
  • Avalon Streaming (Avalon-ST) data path interface connects to client logic.
  • Ready latency of 0 clock cycles for Avalon-ST TX interface.
  • Hardware and software reset control.

Basics

Year IP was first released

2016

Latest version of Intel® Quartus® Prime Design Software supported

18.1

 

Status

Early Access

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim*- Intel FPGA Edition
  • Timing and/or layout constraints
  • Documentation with revision control
  • Readme file

Y

Any additional customer deliverables provided with IP

 

Parameterization GUI allowing end user to configure IP

Y

IP is enabled for Intel FPGA IP Evaluation Mode Support

Y

Source language

Verilog

Testbench language

 

Software drivers provided

N

Driver operating system (OS) support

 

Implementation

User interface

Avalon®-ST (Datapath), Avalon-MM (Management)

IP-XACT metadata

N

Verification

Simulators supported

Mentor Graphics*, Synopsys*, Cadence*

Hardware validated

Intel Arria® 10 GT, Intel Stratix® 10 devices with H-Tile(s)

Industry standard compliance testing performed

N

If Yes, which test(s)?

 

If Yes, on which Intel FPGA device(s)?

 

If Yes, date performed

 

If No, is it planned?

Y

Interoperability

IP has undergone interoperability testing

Y

If yes, on which Intel FPGA device(s)

Intel Arria 10 GT device

Interoperability reports available

N

For technical support on this IP core, please visit the Intel® Premier Support. You can also search for related topics on this function in the Knowledge Center.

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