Intel offers ultimate flexibilty, scalability, and configurability with the 100G Ethernet Soft intellectual property (IP) cores targeted for use in network infrastructure and data center applications. The Low Latency and Legacy Intel
® FPGA IP cores for 100G Ethernet are IEEE 802.3ba-2010 standard compliant and include a media access control (MAC), PHY, comprised of physical coding sublayer (PCS) and physical medium attachment (PMA), an optional forward error correction (FEC) block, timestamping with IEEE 1588v2 support and the capability to drive backplanes on supported Stratix ® and Arria ® FPGAs. The PHY block (PCS-FEC-PMA) is also available as a standalone block in case users want to use their own MAC IP.
The 100GE MAC and PHY function is also available in Hard IP form on Intel Stratix 10 devices with H-Tile(s) and E-Tile(s). More information is available on
Intel Stratix 10 FPGA H-Tile Hard IP for Ethernet IP Core and Intel Stratix 10 FPGA E-Tile Hard IP for Ethernet IP Core pages respectively.
The Intel FPGA IP for 100G Ethernet can be used for any chip-to-chip interconnect, or to interface to copper or optical transceiver modules to drive cabling.
50G Ethernet features
Compliant with the
25G and 50G Ethernet Specification, Draft 1.4 from the 25 Gigabit Ethernet Consortium Supports 64B/66B encoding with data striping and alignment markers to align data
® Memory-Mapped (Avalon-MM) management interface to access the IP control and status registers Avalon Streaming (Avalon-ST) datapath interface connects to client logic with the start of frame in the most significant bit (MSB)
Support for jumbo packets, defined as packets greater than 1,500 bytes
Receiver (RX) cyclic redundancy check (CRC) removal and pass-through control
Transmitter (TX) CRC generation and insertion
RX CRC checking and error reporting
TX error insertion capability
RX and TX preamble pass-through option for applications that require proprietary user management
TX automatic frame padding to meet the 64-byte minimum Ethernet frame length
Hardware and software reset control
MAC provides cut-through frame processing, no store-and-forward capability
Deficit idle counter (DIC) to maintain a 12-byte inter-packet gap (IPG) average
Optional fault signaling: detects and reports local fault and generates remote fault with
802.3ba-2012 Ethernet Standard Clause 66 support Optional serial PMA loopback (TX to RX) at the serial transceiver for self-diagnostic testing
Optional access to Intel FPGA Debug Master Endpoint
Partial reconfiguration of the FPGA fabric
Ready latency of 0 or 3 cycles for Avalon-ST TX interface
Year IP was first released
Latest version of Intel® Quartus® software supported
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim*- Intel FPGA Edition
Timing and/or layout constraints
Documentation with revision control
Any additional customer deliverables provided with IP
Parameterization GUI allowing end user to configure IP
IP is enabled for Intel FPGA IP Evaluation Mode Support
Software drivers provided
Driver operating system (OS) support
®-ST (Datapath), Avalon-MM (Management)
Mentor Graphics*, Synopsys*, Cadence*
Hardware validated Intel Arria
® 10 GT, Intel Stratix® 10 devices with H-Tile(s)
Industry standard compliance testing performed
If Yes, which test(s)?
If Yes, on which Intel FPGA device(s)?
If Yes, date performed
If No, is it planned?
IP has undergone interoperability testing
If yes, on which Intel FPGA device(s)
Arria 10 GT device
Interoperability reports available
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