25G Ethernet MAC and PHY Intel® FPGA IP Core

The 25G Ethernet MAC and PHY Intel® FPGA IP core (soft IP) offers superior performance and scalability and is a cost-efficient solution for supporting the demands of millions of new connected devices for Internet of Things (IoT), data centers, and storage endpoints infrastructures. This intellectual property (IP) core implements the 25G and 50G Ethernet Specification, Draft 1.4 from the 25 Gigabit Ethernet Consortium. The IP core includes an option to support unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012 Ethernet Standard. The media access control (MAC) client side interface for the 25GbE IP core is a 64 bit Avalon® Streaming (Avalon-ST) interface. It maps to one 25.78125 Gbps transceiver. The IP core optionally includes Reed-Solomon forward error correction (FEC) for support of direct attach copper (DAC) cable. 

The 25G Ethernet MAC and PHY Intel FPGA IP core with various optional features is also available as hard IP on Intel Stratix® 10 devices with E-Tiles. More details can be found on the E-Tile Hard IP for Ethernet page.

  • Parameterizable through the IP Catalog available in Intel® Quartus® Prime design software
  • Compliant with the 25G and 50G Ethernet Specification, Draft 1.4 from the 25 Gigabit Ethernet Consortium
  • Designed to the IEEE 802.3ba-2012 High Speed Ethernet Standard (www.ieee.org)
  • Optional support for Reed Solomon Forward Error Correction (RS-FEC) and IEEE 1588v2 time stamping
  • Soft physical coding sublayer (PCS) logic that interfaces seamlessly to Intel FPGA 25.78125 gigabits per second (Gbps) serial transceivers
  • Supports 64B/66B encoding with data striping and alignment markers to align data
  • Avalon® Memory-Mapped (Avalon-MM) management interface to access the IP core control and status registers
  • Avalon-ST datapath interface connects to client logic
  • Includes dynamically-generated example design feature
  • Optional serial physical medium attachment (PMA) loopback (TX to RX) at the serial transceiver for self-diagnostic testing
  • Optional access to Intel FPGA Debug Master Endpoint  

For technical support on this IP core, please visit Intel Premier Support . You can also search for related topics on this function in the Knowledge Base.


Year IP was first released


Latest version of Intel® Quartus® Prime design software supported





Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim*- Intel FPGA Edition
  • Timing and/or layout constraints
  • Documentation with revision control
  • Readme file


Any additional customer deliverables provided with IP


Parameterization GUI allowing end user to configure IP


IP core is enabled for Intel FPGA IP Evaluation Mode Support


Source language


Testbench language


Software drivers provided


Driver operating system (OS) support



User interface

Avalon®-ST (Datapath), Avalon-MM (Management)

IP-XACT metadata



Simulators supported

Mentor Graphics*, Synopsys*, Cadence*

Hardware validated

Intel Arria® 10, Intel Stratix® 10

Industry standard compliance testing performed


If Yes, which test(s)?


If Yes, on which Intel FPGA device(s)?


If Yes, date performed


If No, is it planned?



IP has undergone interoperability testing


If yes, on which Intel FPGA device(s)

Intel Arria 10 GT

Interoperability reports available