This IP core implements the 25G and 50G Ethernet Specification, Draft 1.4 from the 25 Gigabit Ethernet Consortium. The IP core includes an option to support unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012 Ethernet Standard. The media access control (MAC) client side interface for the 25GbE IP core is a 64 bit Avalon® Streaming (Avalon-ST) interface. It maps to one 25.78125 Gbps transceiver. The IP core optionally includes Reed-Solomon forward error correction (FEC) for support of direct attach copper (DAC) cable.
The 25G Ethernet Intel FPGA IP core with various optional features is also available as hard IP on Intel Stratix® 10 devices with E-Tiles. More details can be found on the E-Tile Hard IP for Ethernet page.