Backplane Ethernet 10GBASE-KR PHY Intel® FPGA IP Core

Figure 1. 10GBASE-KR Ethernet PHY Block Diagram

The Backplane Ethernet 10GBASE-KR PHY Intel® FPGA IP core is a transceiver PHY which allows you to instantiate both the hard standard physical coding sublayer (PCS) and the higher performance hard 10G PCS, and hard physical medium attachment (PMA) for a single Backplane Ethernet channel. It implements the functionality described in the IEEE 802.3ap-2007 Standard. Because each instance of the 10GBASE-KR PHY IP core supports a single channel, you can create multi-channel designs by instantiating more than one instance of the core.

  • Integrated 1000BASE-KX / 10GBASE-KR (1G/10Gb) backplane Ethernet PCS and PMA
  • Direct internal interface with Intel FPGA 1G/10GbE media access controller (MAC) for a complete single-chip solution
  • 10GBASE-KR auto-negotiation for negotiating between 1000BASE-KX (1 Gbps Ethernet or 1GbE) and 10GBASE-KR (10 Gbps Ethernet or 10GbE) PHY types per clause 73 of the IEEE 802.3ap-2007 standard
  • Link training to automatically configure the remote link partner transmitter physical media driver (PMD) for the lowest bit error rate (BER) per clause 72 of IEEE 802.3ap-2007 standard
  • Forward error correction (FEC) to minimize retransmission in accordance to IEEE 802.3 and 802.3ba clause 74
  • Internal programmable algorithm for the receiver adaptation process per IEEE 8023.ap clause for ease of use
  • Flexible IP user controls for performance optimization in various system configurations and channels
  • Receiver-link fault status detection
  • Local serial loop-back from transmitter to receiver at the serial transceiver for self test
  • High-performance internal system interfaces
    • GMII and single data rate (SDR) XGMII interfaces to 1G/10GbE MAC, 8 bits at 125 MHz and 72 bits at 156.25 MHz respectively for data transfer
    • Intel FPGA Avalon® Memory-Mapped (PDF) (Avalon-MM) 32 bit interface for slave management

Supported Devices

Typical expected performance and resource utilization figures for this IP core are provided in the V-Series Transceiver PHY IP Core User Guide (PDF).


Year IP was first released


Latest version of Intel® Quartus®  Prime design software supported





Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim*-Intel FPGA Edition
  • Timing and/or layout constraints
  • Documentation with revision control
  • Readme file


Any additional customer deliverables provided with IP


Parameterization GUI allowing end user to configure IP


IP core is enabled for Intel FPGA IP Evaluation Mode Support


Source language


Testbench language


Software drivers provided


Driver OS Support



User interface


IP-XACT metadata



Simulators supported

Mentor Graphics*, Synopsys*, Cadence*

Hardware validated

Intel Arria® 10, Intel Stratix 10

Industry standard compliance testing performed


If Yes, which test(s)?


If Yes, on which Intel FPGA device(s)?


If Yes, date performed


If No, is it planned?



IP has undergone interoperability testing


If yes, on which Intel FPGA device(s)


Interoperability reports available


For technical support on this IP core, visit Intel Premier Support. You can also search for related topics on this function in the Knowledge Center.