The Backplane Ethernet 10GBASE-KR PHY Intel® FPGA Intellectual Property (IP) core is a transceiver PHY that allows you to instantiate both the hard standard physical coding sublayer (PCS) and the higher performance hard 10G PCS, and hard physical medium attachment (PMA) for a single Backplane Ethernet channel. It implements the functionality described in the IEEE 802.3ap-2007 standard. Because each instance of the 10GBASE-KR PHY IP core supports a single channel, you can create multichannel designs by instantiating more than one instance of the core.
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