Interlaken Look-Aside Intel® FPGA IP Core

Figure 1. Typical Application Block Diagram

300G Interlaken Look-Aside IP Performance Interop with TE Connectivity Using Intel® Arria® 10 Device


Automated Generation of SignalTap II Files for Arria 10 IP Core IP Debug Feature


Push-button Hardware Design Examples in Intel® Quartus® Prime Software


Interlaken Look-Aside is a scalable protocol that allows interoperability between a datapath device and a look-aside coprocessor with packet transfer rates from 10 Gbps to 300 Gbps and beyond. The Interlaken Look-Aside Intel® FPGA intellectual property (IP) core continues to scale with today’s demand for more bandwidth and higher performance needs. Intel has been a part of the Interlaken Alliance since its inception in 2007 and continues to innovate with new protocol features to provide customers with robust and easy-to-implement Interlaken Look-Aside IP solutions. The Interlaken Look-Aside Intel FPGA IP core offer a wide range of bandwidths up to 300G.

Intel and Cavium Team Up to Provide Pre-Verified Packet Classification Solution

The Interlaken Look-Aside Intel FPGA IP core on an Intel Stratix® V FPGA with Cavium’s NEURON Search* Processor provides customers a proven packet classification solution that can easily be implemented on any networking or data center platform.

To further simplify our customers’ decision-making process, Intel and Cavium have generated an interoperability report that details the various interoperability modes and performance metrics that can be achieved with this complete, high-performance chipset. Contact your sales person for a copy of this report.

Figure 2. Intel and Cavium* Interlaken Look-Aside Connectivity Setup

Intel and Cavium Connectivity System Overview

System Overview Details
Hardware
  • Intel: Stratix® V GX device (5SGXMA7)
  • Cavium: NEURON Search processor evaluation board (EBA-NSP)
Interlaken Look-Aside IP configuration setup
  • 4 lanes x 10.3125 Gbps
  • 8 lanes x 10.3125 Gbps
Results
  • Successfully passing traffic reliably using various packet sizes
  • Logical channel processing validated
  • Maximum packet throughput = 614 Mpps for packets under 12 bytes
  • Average Latency = 256 nsec (on Intel FPGA ILA IP)

Intel FPGA Interlaken Look-Aside IP Solution

The Interlaken Look-Aside Intel® FPGA IP core includes Intel's technology-leading transceivers: physical medium attachment (PMA), physical coding sublayer (PCS), and media access control (MAC) layers. The PCS and PMA layers are hardened within the Intel Stratix® 10, Intel Arria® 10, Stratix V, and Arria V FPGAs. The Interlaken Look-Aside IP core has been through extensive simulation verification and has been proven to work on multiple internal and customer platforms. Intel continues to set up interoperability activities with leading ASSP vendors for next-generation platforms. The Intel FPGA IP Evaluation Mode feature allows the user to evaluation the IP without needing a license.

Intel offers customized Interlaken Look-Aside IP solutions. For more information, please contact your local sales representative.

  • Data rate selection up to 12.5 Gbps
  • Multi-lane configuration up to 24 lanes
  • Packet mode support
  • Low-latency transmit and receive datapaths
  • BurstShort support: 8 bytes or higher
  • Up to two logical channels
  • In-band flow control
  • Fully integrated IP (MAC, PCS, and PMA layers)
  • Tunable pre-emphasis and equalization settings
  • Custom IP deliveries available to optimize for various application needs

Interlaken Look-Aside IP Quality Metrics

Basics

Year IP was first released

2012

Latest version of Intel® Quartus® software supported

18.1

Status

Customization Request1

Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim*-Intel FPGA Edition
  • Timing and/or layout constraints
  • Documentation with revision control
  • Readme file
Y for all, except for support of ModelSim - Intel FPGA Edition

Any additional customer deliverables provided with IP

Testbench and Design Examples

Parameterization GUI allowing end user to configure IP

N

IP core is enabled for the Intel FPGA IP Evaluation Mode Support

N

Source language

Verilog

Testbench language

Verilog

Software drivers provided

N

Driver operating system (OS) support

N/A

Implementation

User interface

Avalon® Memory-Mapped

IP-XACT metadata

N

Verification

Simulators supported

NCSim, ModelSim, VCS/VCSMX

Hardware validated

Y, Arria® 10 Transceiver Signal Integrity Development Kit

Industry-standard compliance testing performed

N/A

If Yes, which test(s)?

N/A

If Yes, on which Intel FPGA device(s)?

N/A

If Yes, date performed

N/A

If No, is it planned?

N

Interoperability

IP has undergone interoperability testing

Y

If yes, on which Intel FPGA device(s)

Stratix® V

Interoperability reports available

Y, Cavium NEURON Search* Processor

  1. Please contact your local sales representative.

For technical support on this IP core, please visit Intel® Premier Support. You may also search for related topics on this function in the Knowledge Center.