Interlaken Look-Aside Intel® FPGA IP

Interlaken Look-Aside Interconnect Protocol

Interlaken Look-Aside is a scalable protocol that allows interoperability between a datapath device and a look-aside coprocessor for short, transaction-related transfers. A look-aside coprocessor is connected "to the side" of the datapath, and is not in-line of the main datapath of the switch, router, or other networking device. Interlaken Look-Aside is not directly compatible with Interlaken and can be considered a different operational mode.

The Interlaken Look-Aside IP core is suited for coprocessing packet classification typically used for networking applications such as: Quality of service routing, traffic profiling, and firewall functions. The IP's low-latency packet interface, coupled with its efficient data processing capability, enables a high degree of design scalability for emerging network applications.

This IP core includes Intel's technology-leading transceivers:

  • Physical medium attachment (PMA)
  • Physical coding sublayer (PCS)
  • Media access control (MAC) layers. 

The PCS and PMA layers are hardened within the Intel® Stratix® 10, Intel® Arria® 10, Stratix V, and Arria V FPGAs.

Features

 
Intel has been a part of the Interlaken Alliance since its inception in 2007 and continues to innovate with new protocol features to provide customers with robust and easy-to-implement Interlaken Look-Aside IP solutions. The Interlaken Look-Aside Intel FPGA IP core offers a wide range of bandwidths up to 300G.
 
The Interlaken Look-Aside IP core is Interlaken Look-Aside Protocol Definition v1.1 compliant and allows system developers to eliminate the computational bottlenecks associated with older, packet classification methods. Intel also offers customized Interlaken Look-Aside IP solutions. For more information, please contact your local sales representative.
 
  • Data rate selection up to 25 Gbps
  • Multi-lane configuration up to 24 lanes
  • Packet mode support
  • Low-latency transmit and receive datapaths
  • BurstShort support: 8 bytes or higher
  • Up to two logical channels
  • In-band flow control
  • Fully integrated IP (MAC, PCS, and PMA layers)
  • Tunable pre-emphasis and equalization settings
  • Custom IP deliveries available to optimize for various application needs
  • Available through the IP catalog in the Intel® Quartus® Prime Pro Edition software
Intel and Cavium Interlaken Look-Aside Connectivity Setup

Intel and Cavium Team Up to Provide Pre-Verified Packet Classification Solution

The Interlaken Look-Aside Intel FPGA IP core on a Stratix® V FPGA with Cavium’s NEURON Search Processor provides customers a proven packet classification solution that can easily be implemented on any networking or data center platform.

To further simplify our customers’ decision-making process, Intel and Cavium have generated an interoperability report that details the various interoperability modes and performance metrics that can be achieved with this complete, high-performance chipset. Contact your sales person for a copy of this report.

Intel and Cavium Connectivity System Overview

System Overview Details
Hardware
  • Intel: Stratix® V GX device (5SGXMA7)
  • Cavium: NEURON Search processor evaluation board (EBA-NSP)
Interlaken Look-Aside IP configuration setup
  • 4 lanes x 10.3125 Gbps
  • 8 lanes x 10.3125 Gbps
Results
  • Successfully passing traffic reliably using various packet sizes
  • Logical channel processing validated
  • Maximum packet throughput = 614 Mpps for packets under 12 bytes
  • Average latency = 256 nsec (on Intel FPGA ILA IP)

IP Quality Metrics

Basics

Year IP was first released

2012

Latest version of Intel® Quartus® Prime software supported

20.2

Status

Customization Request1

Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Timing and/or layout constraints
  • Documentation with revision control
Y for all

Any additional customer deliverables provided with IP

Testbench and Design Examples

Parameterization GUI allowing end user to configure IP

N

IP core is enabled for the Intel FPGA IP Evaluation Mode Support

N

Source language

Verilog

Testbench language

Verilog

Software drivers provided

N

Driver operating system (OS) support

N/A

Implementation

User interface

Avalon® ST - like

IP-XACT metadata

N

Verification

Simulators supported

NCSim, ModelSim, VCS/VCSMX, Xcelium

Hardware validated

Y, Intel® Arria® 10 FPGA Transceiver Signal Integrity Development Kit,

Intel® Stratix® 10 FPGA Signal Integrity Development Kit, 

Intel® Agilex™ FPGA F-Series Transceiver-SoC Development Kit

Industry-standard compliance testing performed

N/A

If Yes, which test(s)?

N/A

If Yes, on which Intel FPGA(s)?

N/A

If Yes, date performed

N/A

If No, is it planned?

N

Interoperability

IP has undergone interoperability testing

N

If yes, on which Intel FPGA(s)

 

Interoperability reports available

 N

  1. Please contact your local sales representative.

Automated Generation of Signal Tap II Files for Intel Arria 10


Push-button Hardware Design Examples in Intel® Quartus® Prime


300G Interlaken Look-Aside IP Performance Interop Using Intel® Arria® 10 Device


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Related Links

 

For technical support on this IP core, please visit Intel® Premier Support. You may also search for related topics on this function in the Knowledge Center.

† Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase.  For more complete information about performance and benchmark results, visit www.intel.com/benchmarks.Intel and Quartus are trademarks of Intel Corporation or its subsidiaries in the US and/or other countries.