Intel Agilex F-Tile Ethernet Hard IP

Hardened Ethernet Protocol Stack

The Intel® Agilex™ FPGA F-Tile incorporates a fracturable, configurable, hardened Ethernet protocol stack for supporting rates from 10G to 400G, compatible with IEEE 802.3 specification, and other related Ethernet Consortium specifications.

The intellectual property (IP) core implements Ethernet at data rates of 10 Gbps, 25 Gbps, 40 Gbps, 50 Gbps, 100 Gbps, 200 Gbps and 400 Gbps. The IP core is included in the IP library and is available from the IP Catalog.

 

 

 

The IP core is available in multiple variants providing different combinations of Ethernet channels and features. These include optional Reed-Solomon Forward Error Correction (RSFEC) and optional IEEE 1588v2 Precision Time Protocol (PTP). The user can choose a media access control (MAC) and a physical coding sublayer (PCS) variation, a PCS-only variation, a Flexible Ethernet (FlexE) variation, or an Optical Transport Network (OTN) variation.

The following table gives an overview of various features supported by the F-Tile Ethernet Hard IP.

Ethernet Mode

Modulation

PMA

Type

FEC Selection

MAC AvST

MAC

Seg

PCS (MII)

PCS (OTN/

FlexE)

PTP

AN/LT

No FEC

CL74

CL91

CL134

ETC

10GE-1

NRZ

FGT

_

_

_

_

25GE-1

NRZ

FGT FHT

_

40GE-4

NRZ

FGT

_

_

_

_

_

_

50GE-2

NRZ

FGT FHT

_

_

_

50GE-1

PAM4

FGT FHT

_

_

_

100GE-4

NRZ

FGT FHT

_

_

100GE-2

PAM4

FGT FHT

_

_

_

100GE-1

PAM4

FHT

_

_

_

_

200GE-8

NRZ

FGT

_

_

_

_

_

_

200GE-4

PAM4

FGT FHT

_

_

_

_

200GE-2

PAM4

FHT

_

_

_

_

_

400GE-8

PAM4

FGT

_

_

_

_

400GE-4

PAM4

FHT

_

_

_

_

_

FEC Selection supports the following FEC types:

  • No FEC: No FEC
  • CL74: IEEE 802.3 BASE-R Firecode (CL 74) 
  • CL91: IEEE 802.3 RS( 528, 514) (CL91) 
  • CL134 : IEEE 802 . 3 RS(544,514) (CL134)
  • ETC : Ethernet Technology Consortium ETC RS(272, 258)

Abbreviations:

  • MAC AvST : MAC Avalon® streaming interface 
  • MAC Seg: MAC Segmented

 

Features

 

The hard IP core enables all IEEE and Consortium Ethernet modes for the following rates: 10G, 25G, 40G, 100G, 200G and 400G.The MAC provides cut-through frame processing to optimize latency and supports full wire line speed with a 64-byte frame length and back-to-back or mixed-length traffic with no dropped packets. All IP core variations are in full-duplex mode.

The IP features are listed below:

PHY

  • Supports 10GE-1, 25GE-1, 40GE-4, 50GE-1, 50GE-2, 100GE-1, 100GE-2, 100GE-4, 200GE-2, 200GE-4, 200GE-8, 400GE-4, 400GE-8 modes
    • 10GBASE-KR, 10GBASE-CR, 10GBASE-LR
    • 25GBASE-KR, 25GBASE-CR, 25GBASE-R, 25GAUI-1
    • 40GBASE-KR4, 40GBASE-CR4, 40GBASE-R4
    • 50GBASE-KR1, 50GBASE-CR1, 50GBASE-KR2, 50GBASE-CR2, 50GAUI-1, 50GAUI-2
    • 100GBASE-KR1, 100GBASE-CR1, 100GBASE-KR2, 100GBASE-CR2, 100GBASE-KR4, 100GBASE-CR4, 100GAUI-1, 100GAUI-2, 100GAUI-4, CAUI-2, CAUI-4
    • 200GBASE-KR2, 200GBASE-CR2, 200GBASE-KR4, 200GBASE-CR4, 200GAUI-2, 200GAUI-4, 200GAUI-8
    • 400GBASE-KR4, 400GBASE-CR4, 400GAUI-4, 400GBASE-KR8, 400GBASE-CR8, 400GAUI-8
  • Transceiver lanes operating at 10.3125 Gbps, 25.78125 Gbps, 26.5625 Gbps, 53.125 Gbps or 106.25 Gbps to support various Ethernet modes
  • Supports NRZ and PAM4 modes
  • Supports 64B/66B encoding with data striping and alignment markers to align data from multiple lanes
  • Optional Reed-Solomon forward error correction RS-FEC (528,514) usually termed KR-FEC or RS-FEC (544,514) usually termed KP-FEC
  • Firecode FEC (CL74) support
  • Auto-negotiation (AN) as defined in IEEE Standard 802.3-2915 Clause 73 and the 25G Ethernet Consortium Schedule Draft 1.6
  • Link training (LT) as defined in IEEE Standard 802.3-2915 Clauses 92 and 93, and the 25G Ethernet Consortium Schedule Draft 1.6
  • Optional deficit idle counter (DIC) options to maintain a finely controlled 8-byte, 10-byte, or 12-byte interpacket gap (IPG) minimum average, or allow the user to drive the IPG from the client interface
  • Receiver (RX) skew variation tolerance that exceeds the IEEE 802.3-2015 High-Speed Ethernet Standard Clause 80.5 requirements

Frame structure control

  • Support for jumbo packets
  • RX cyclic redundancy check (CRC) pass-through control
  • 1000 bits RX PCS lane skew tolerance for 100G links, which exceeds IEEE 802.3-2015 High-Speed Ethernet Standard Clause 82.2.12 requirements
  • Optional per-packet transceiver (TX) CRC generation and insertion
  • RX and TX preamble pass-through options for applications that require proprietary user management information transfer
  • Optional TX MAC source address insertion
  • TX automatic frame padding to meet the 64-byte minimum Ethernet frame length on the Ethernet link. Optional per-packet disabling of this feature.
  • TX error insertion capability supports client invalidation of in-progress input to TX client interface

Frame monitoring and statistics

  • RX CRC checking and error reporting
  • Optional RX strict Start Frame Delimiter (SFD) checking to IEEE specification
  • Optional RX strict preamble checking to IEEE specification
  • RX malformed packet checking to IEEE specification
  • Received control frame type indication
  • Statistics counters
  • Snapshot feature for precisely timed capture of statistics counter values
  • Optional fault signaling detects and reports local fault and generates a remote fault with support for a unidirectional link fault defined in IEEE 802.3-2015 High-Speed Ethernet Standard Clause 66

Flow control

  • Optional IEEE 802.3-2018 Ethernet Standard Clause 31 Ethernet flow control operation using the pause registers or pause interface
  • Optional priority-based flow control that complies with the IEEE Standard 802.1Q-2014 — Amendment 17: Priority-based Flow Control
  • Pause frame filtering control
  • Software can dynamically toggle local TX MAC data flow to selectively cut off input flow

Precision Time Protocol (PTP)

  • Optional support for the IEEE Standard 1588v2 PTP
  • 1-step (1588v1 and 1588v2), and 2-step TX timestamps
  • Support for PTP headers in a variety of frame formats, including Ethernet encapsulation, UDP in IPv4, and UDP in IPv6
  • Support for checksum zero and checksum extension byte calculations
  • Support for correction field operations
  • Programmable extra latency and asymmetric latency

OTN

  • Optional 25/50GbE constant bit rate (CBR) with TX and RX PCS 66-bit encoding and scrambling disabled
  • Optional 25/50GbE CBR with full MAC and PCS 66-bit features

User system interface

  • Avalon® Memory-Mapped (Avalon-MM) management interface to access the IP core control and status registers
  • Avalon-ST datapath interface connects the MAC to client logic with the start of frame in the most significant byte (MSB) in MAC with PCS variations. Interface for 100G channel has 512 bits; the 10/25G channels use 64 bits when the MAC layer is enabled (AVST interface is available only for 10 G to 100G)
  • MAC Avalon-ST Interface is available for 10G to 100G
  • MAC segmented interface is available for 10G to 400G
  • MII datapath interface connects the PCS to client logic in PCS-only variations
  • Hardware and software reset control
  • Supports Synchronous Ethernet (SyncE) by providing a clock data recovery (CDR) output signal to the device fabric

Debug and testability

  • Bit-interleaved parity error counters to monitor bit errors per PCS lane
  • RX PCS error block counters to monitor errors during and between frames
  • Malformed and dropped packet counters
  • High bit error rate (BER) detection to monitor link BER over all PCS lanes
  • Optional scrambled idle test pattern generation and checking
  • Snapshot feature for precisely timed capture of statistics counter values
  • TX error insertion capability to support test and debug
  • Supports 10G-1, 25G-1, 50G-1, 50G-2, 100G-1, 100G-2, 100G-4,200G-4, 200G-8, 400G-4 modes 

IP Quality Metrics

Basics

Year IP was first released

2021

Latest version of Intel® Quartus® design software supported

21.1

Status

Production

Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim*- Intel FPGA Edition
  • Timing and/or layout constraints
  • Documentation with revision control
  • Readme.txt file

Y

Any additional customer deliverables provided with IP

N/A

Parameterization GUI allowing end user to configure IP

Yes

IP core is enabled for Intel FPGA IP Evaluation Mode Support

Yes

Source language

Verilog

Testbench language

Verilog

Software drivers provided

 

Driver OS Support

 

Implementation

User interface

Avalon®-ST(Datapath(, Avalon®-MM(Management)

IP-XACT metadata

Yes

Verification

Simulators supported

Synopsys VCS

Hardware validated

 

Industry standard compliance testing performed

Planned for future

If Yes, which tests?

 

If Yes, on which Intel FPGAs?

 

If Yes, date performed

 

If No, is it planned?

Planned

Interoperability

IP has undergone interoperability testing

 

If yes, on which Intel FPGAs?

 

Interoperability reports available

 

Find the IP you need for Intel FPGAs, SoCs, and Structured ASICs

For a complete list of Intel and third-party IPs, please visit the Find IP page. 

Related Links

For technical support on this IP core, visit the Intel® FPGA IP for Ethernet Support Center page. For additional support, please visit Intel Premier Support. You may also search for related topics on this function in the Knowledge Base.

† Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase.  For more complete information about performance and benchmark results, visit www.intel.com/benchmarks.Intel and Quartus are trademarks of Intel Corporation or its subsidiaries in the US and/or other countries.