Intel® Stratix® 10 FPGA E-Tile Hard IP for Ethernet Intel FPGA IP Core

The Intel® Stratix® 10 FPGA E-Tile incorporates a configurable, hardened Ethernet protocol stack compatible with the IEEE 802.3 High-Speed Ethernet Standard and the 25G and 50G Ethernet Specification, Draft 1.6 from the 25G Ethernet Consortium.

The intellectual property (IP) core provides access to this hard IP at data rates of 10 Gbps, 25 Gbps, and 100 Gbps. The IP core is included in the IP library and is available from the IP Catalog. 

The IP core is available in multiple variants, each providing a different combination of Ethernet channels and features.

  • One to four 10GbE/25GbE channels with optional Reed-Solomon Forward Error Correction (RS-FEC)
  • 100G channel with optional RS-FEC for either CAUI-4 or CAUI-2 mode
  • Dynamic configuration between one to four single 10GbE/25GbE channels or one 100GbE channel

All the variants provide an optional IEEE 1588v2 Precision Time Protocol (PTP). The user can choose a media access control (MAC) and a physical coding sublayer (PCS) variation, a PCS-only variation, a Flexible Ethernet (FlexE) variation, or an Optical Transport Network (OTN) variation.

Ethernet Protocols

Ethernet IP Protocol Number of Lanes and Line Rate
100GbE 100GBASE-KR4 4x25.78125 Gbps non-return-to-zero (NRZ) for copper backplane
100GBASE-CR4 4x25.78125 Gbps NRZ for direct-attach copper cable
CAUI-4 4x25.78125 Gbps NRZ for low-loss links: Chip-to-chip or chip-to-module
CAUI-2 2x53.1 Gbps PAM4 for low-loss links: Chip-to-chip, chip-to-module, and  digital-to-analog converter (DAC)
25GbE 25GBASE-KR Gbps for backplane
25GBASE-CR Gbps for direct-attach copper cable
25GBASE-R AUI Gbps for low-loss connections to external PHY modules
25GBASE-R Consortium Link Gbps based on the 25G/50G consortium specification
10GbE 10GBASE-KR 10.3125 Gbps for backplane
10GBASE-CR 10.3125 Gbps Lanes for direct attach copper cable

The IP core is designed to the IEEE 802.3-2015 High-Speed Ethernet Standard, available on the IEEE website (www.ieee.org), and the 25G, 50G Ethernet Specification, Draft 1.6, available from the 25 Gigabit Ethernet Consortium. The MAC provides cut-through frame processing to optimize latency, and supports full wire line speed with a 64-byte frame length and back-to-back or mixed-length traffic with no dropped packets. All IP core variations are in full-duplex mode. The IP features are listed below:

PHY: 

  • CAUI external interface consisting of four FPGA hard serial transceiver lanes operating at 25.78125 Gbps
  • CAUI-2 external interface with two transceiver lanes operating at 53.125 Gbps with PAM4 encoding
  • 25G CAUI external interface with one transceiver lane operating at 25.78125 Gbps
  • 10G CAUI external interface with one transceiver lane operating at 10.3125 Gbps
  • Supports CAUI-4 links based on 64B/66B encoding with data striping and alignment markers to align data from multiple lanes
  • Optional Reed-Solomon forward error correction RS-FEC (528,514) or RS-FEC (544,514)
  • Supports 10G, 25G, and 100G variations
  • Auto-negotiation (AN) as defined in IEEE Standard 802.3-2915 Clause 73 and the 25G Ethernet Consortium Schedule Draft 1.6
  • Link training (LT) as defined in IEEE Standard 802.3-2915 Clauses 92 and 93, and the 25G Ethernet Consortium Schedule Draft 1.6
  • Optional deficit idle counter (DIC) options to maintain a finely controlled 8-byte, 10-byte, or 12-byte interpacket gap (IPG) minimum average, or allow the user to drive the IPG from the client interface
  • Receiver (RX) skew variation tolerance that exceeds the IEEE 802.3-2015 High-Speed Ethernet Standard Clause 80.5 requirements

Frame structure control:

  • Support for jumbo packets
  • RX cyclic redundancy check (CRC) pass-through control
  • 1000 bits RX PCS lane skew tolerance for 100G links, which exceeds IEEE 802.3-2015 High-Speed Ethernet Standard Clause 82.2.12 requirements
  • Optional per-packet transceiver (TX) CRC generation and insertion
  • RX and TX preamble pass-through options for applications that require proprietary user management information transfer
  • Optional TX MAC source address insertion
  • TX automatic frame padding to meet the 64-byte minimum Ethernet frame length on the Ethernet link. Optional per-packet disabling of this feature.
  • TX error insertion capability supports client invalidation of in-progress input to TX client interface

Frame monitoring and statistics

  • RX CRC checking and error reporting
  • Optional RX strict Start Frame Delimiter (SFD) checking to IEEE specification
  • Optional RX strict preamble checking to IEEE specification
  • RX malformed packet checking to IEEE specification
  • Received control frame type indication
  • Statistics counters
  • Snapshot feature for precisely-timed capture of statistics counter values
  • Optional fault signaling: detects and reports local fault and generates a remote fault with support for a unidirectional link fault defined in IEEE 802.3-2015 High-Speed Ethernet Standard Clause 66

Flow control:

  • Optional IEEE 802.3-2015 Ethernet Standard Clause 31 Ethernet flow control operation using the pause registers or pause interface
  • Optional priority-based flow control that complies with the IEEE Standard 802.1Q-2014 — Amendment 17: Priority-based Flow Control
  • Pause frame filtering control
  • Software can dynamically toggle local TX MAC data flow to selectively cut off input flow

Precision Time Protocol (PTP):

  • Optional support for the IEEE Standard 1588v2 PTP 
  • 1-step (1588v1 and 1588v2), and 2-step TX timestamps
  • Support for PTP headers in a variety of frame formats, including Ethernet encapsulation, UDP in IPv4, and UDP in IPv6
  • Support for checksum zero and checksum extension byte calculations
  • Support for correction field operations
  • Programmable extra latency and asymmetric latency

OTN:

  • Optional 25/50GbE constant bit rate (CBR) with TX and RX PCS 66-bit encoding and scrambling disabled
  • Optional 25/50GbE CBR with full MAC and PCS 66-bit features

User system interface:

  • Avalon® Memory-Mapped (Avalon-MM) management interface to access the IP core control and status registers
  • Avalon-ST datapath interface connects the MAC to client logic with the start of frame in the most significant byte (MSB) in MAC with PCS variations. Interface for 100G channel has 512 bits; the 10/25G channels use 64 bits when the MAC layer is enabled
  • MII datapath interface connects the PCS to client logic in PCS-only variations. The interface for 100G variants has 256 bits of data and 32 bits of control; the interface for 10G/25G variants has 64 bits of data and 8 bits of control
  • Hardware and software reset control
  • Supports Synchronous Ethernet (SyncE) by providing a clock data recovery (CDR) output signal to the device fabric

Debug and testability:

  • Optional serial PMA loopback (TX to RX) at the serial transceiver for self-diagnostic testing
  • Optional parallel loopback (TX to RX) at the MAC or at the PCS for self-diagnostic testing
  • Bit-interleaved parity error counters to monitor bit errors per PCS lane
  • RX PCS error block counters to monitor errors during and between frames
  • Malformed and dropped packet counters
  • High bit error rate (BER) detection to monitor link BER over all PCS lanes
  • Optional scrambled idle test pattern generation and checking
  • Snapshot feature for precisely timed capture of statistics counter values
  • TX error insertion capability to support test and debug

Intel® Stratix® 10 FPGAs with E-Tiles (Intel Stratix 10 TX and Intel Stratix 10 MX)

Basics

Year IP was first released

2018

Latest version of Intel® Quartus® design software supported

18.1

Status

ES

Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim*- Intel FPGA Edition
  • Timing and/or layout constraints
  • Documentation with revision control
  • Readme.txt file

Y

Any additional customer deliverables provided with IP

N/A

Parameterization GUI allowing end user to configure IP

Y

IP core is enabled for Intel FPGA IP Evaluation Mode Support

Y

Source language

Verilog

Testbench language

N/A

Software drivers provided

N

Driver OS Support

N/A

Implementation

User interface

Avalon®-ST (Datapath), Avalon-MM (Management)

IP-XACT metadata

N

Verification

Simulators supported

Mentor Graphics*, Synopsys*, Cadence*

Hardware validated

Intel Stratix® 10

Industry standard compliance testing performed

N

If Yes, which tests?

N/A

If Yes, on which Intel FPGAs?

N/A

If Yes, date performed

N/A

If No, is it planned?

Y

Interoperability

IP has undergone interoperability testing

Y

If yes, on which Intel FPGAs?

Stratix® 10 TX

Interoperability reports available

N

For technical support on this IP core, visit the Intel® FPGA IP for Ethernet Support Center page. For additional support, please visit Intel Premier Support. You may also search for related topics on this function in the Knowledge Base.

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*Intel Ships Industry’s First 58G PAM4-Capable FPGA Built for Multi-Terabit Network Infrastructure and NFV