The Intel® Agilex™ and Intel Stratix® 10 FPGA E-Tile incorporates a configurable, hardened Ethernet protocol stack compatible with the IEEE 802.3 High-Speed Ethernet Standard and the 25G and 50G Ethernet Specification, Draft 1.6 from the 25G Ethernet Consortium. The Intellectual Property (IP) core provides access to this hard IP at data rates of 10 Gbps, 25 Gbps, and 100 Gbps.
The IP core is available in multiple variants, each providing a different combination of Ethernet channels and features.
- One to four 10GbE/25GbE channels with optional Reed-Solomon Forward Error Correction (RS-FEC)
- 100G channel with optional RS-FEC for either CAUI-4 or CAUI-2 mode
- Dynamic configuration between one to four single 10GbE/25GbE channels or one 100GbE channel
All the variants provide an optional IEEE 1588v2 Precision Time Protocol (PTP). The user can choose a media access control (MAC) and a physical coding sublayer (PCS) variation, a PCS-only variation, a Flexible Ethernet (FlexE) variation, or an Optical Transport Network (OTN) variation.