The Common Public Radio Interface (CPRI) Intel® FPGA IP core implements the CPRI Specification V7.0 (2015-10-09). CPRI is a high-speed serial interface for network radio equipment controllers (REC) to receive data from and provide data to remote radio equipment (RE).

The CPRI Intel® FPGA IP core targets high-performance, remote radio network applications. You can configure the CPRI Intel® FPGA IP core as an RE or an REC.

Please contact your local sales representative for more information.

CPRI Intel FPGA IP Core Supported Features


The CPRI Intel® FPGA IP core offers the following features:

  • Compliant with the Common Public Radio Interface (CPRI) Specification v7.0 (2015-10-09) Interface Specification available on the CPRI Industry Initiative website (www.cpri.info).
  • Supports radio equipment controller (REC) and radio equipment (RE) module configurations.
  • Configurable CPRI communication line bit rate (to 0.6144, 1.2288, 2.4576, 3.0720, 4.9152, 6.144, 8.11008, 9.8304, 10.1376, 12.16512 or 24.33024 Gbps) using Intel® FPGA on-chip high-speed transceivers.
  • CPRI line bit rate auto-rate negotiation support.
  • CPRI Intel® FPGA IP core variations that target an Intel® Stratix® 10 device with 24.33024 Gbps line rate includes a Reed-Solomon Forward Error Correction (RS-FEC) block. This block correct the errors on receiver side.
  • Configurable and run-time programmable synchronization mode: master port or slave port on a CPRI link.
  • Scrambling and descrambling at 8.11008, 10.1376, 12.16512 and 24.33024 Gbps.Optional scrambling and descrambling at 4.9152, 6.1440, and 9.8304 Gbps.Transmitter (Tx) and receiver (Rx) deterministic latency and delay measurement and calibration. Note: Compliant with the CPRI Specification requirements R-19, R-20, R-20A, R-21, amd R-21A.
  • Optional support for single-trip delay calibration.
  • Optional round-trip delay calibration.
  • L1 link status and alarm (Z.130.0) control and status monitoring.
  • Access to all Vendor Specific data.
  • Diagnostic parallel reverse loopback paths.
  • Diagnostic serial and parallel forward loopback paths.
  • Diagnostic stand-alone slave testing mode.
  • Register access interface to external or on-chip processor, using the Intel® Avalon® Memory-Mapped (Avalon-MM) interconnect specification.
  • Optional auxiliary (AUX) interface for full access to raw CPRI frame. Provides direct access to full radioframe, synchronizes the frame position with timing references, and enables routing application support from slave to master ports to implement daisy-chain topologies.
  • Optional choice of IEEE 802.3 100BASE-X compliant 10/100 Mbps MII or 1000BASE-X compliant 1Gbps GMII for Ethernet frame access.
  • Optional direct I/Q access interface enables integration of all user-defined air standard I/Q mapping schemes.
  • Optional external I/Q mapper and demapper modules with reference design support.
  • Optional external I/Q compression and decompression modules with reference design support.
  • Optional vendor specific data access interfaces provide direct access to Vendor Specific (VS), Control AxC (Ctrl_AxC), and Real-time Vendor Specific (RTVS) subchannels.
  • Optional HDLC serial interface provides direct access to slow control and management subchannels.
  • Optional L1 inband interface provides direct access to Z.130.0 link status and alarm control word.

CPRI Intel® FPGA IP Core Performance: Device and Transceiver Speed Grade Support

Lower device speed grade numbers correspond to faster devices. The entry -x indicates that both the industrial speed grade Ix and the commercial speed grade Cx are supported for this device family and CPRI line bit rate. Table entries show slowest supported device speed grade / supported transceiver speed grade.

Device Family CPRI Line Bit Rate (Gbps)
0.6144 1.2288 2.4576 3.072 4.9152 6.1440 8.11008 9.8304 10.1376 12.16512  24.33024 
Intel® Stratix® 10 FPGA 1 -2 / -3 -2 / -2 
Intel® Arria® 10 FPGA 1 -3 / -4
Intel® Stratix® V GT -3 / H3 -2 / H2
Intel® Stratix® V GX -4 / H3 -2 / H2
Intel® Arria® V GZ -4 / H3 -3 / H2 1
Intel® Arria® V GX -6 / H6 -5 / H4 -5 / H4 1
Intel® Arria® V GT -5/H3 1
Intel® Cyclone® V GT -7 / H5 1
Intel® Cyclone® V GX -8 / H7 -7 / H6 1

1 The CPRI v6.0 Intel FPGA IP core does not support this CPRI line bit rate for this device family.