The Intel® FPGA Intellectual Property (IP) for Common Public Radio Interface (CPRI) v6.0 (IP-CPRI-v6) implements the CPRI Specification V6.0 (2013-08-30). CPRI is a high-speed serial interface for network radio equipment controllers (REC) to receive data from and provide data to remote radio equipment (RE). The CPRI v6.0 IP core targets high-performance, remote, radio network applications. You can configure the CPRI v6.0 IP core as an RE or an REC.
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The CPRI v6.0 IP core oﬀers the following features:
Compliant with the Common Public Radio Interface (CPRI) Specification V6.0 (2013-08-30) Interface Specification available on the CPRI Industry Initiative website (www.cpri.info)
Supports REC and RE module configurations
Supports the following CPRI link features:
Configurable CPRI communication line bit rate (to 0.6144, 1.2288, 2.4576, 3.0720, 4.9152, 6.144, 8.11008, 9.8304, or 10.1376 Gbps) using Intel FPGA on-chip high-speed transceivers
CPRI line bit rate auto-rate negotiation support
Configurable and run-time programmable synchronization mode: master port or slave port on a CPRI link
Scrambling and descrambling at 8.11008 and 10.1376 Gbps
Optional scrambling and descrambling at 4.9152, 6.1440, and 9.8304 Gbps
Transmitter (TX) and receiver (RX) delay measurement and calibration
Optional support for single-trip delay calibration
Optional round-trip delay calibration
L1 link status and alarm (Z.130.0) control and status monitoring
Access to all vendor-specific data
Diagnostic parallel reverse loopback paths
Diagnostic serial and parallel forward loopback paths
Diagnostic stand-alone slave testing mode
CPRI v6.0 IP Core Performance: Device and Transceiver Speed Grade Support
Lower device speed grade numbers correspond to faster devices. The entry -x indicates that both the industrial speed grade Ix and the commercial speed grade Cx are supported for this device family and CPRI line bit rate. Table entries show slowest supported device speed grade or supported transceiver speed grade.