CPRI Intel® FPGA IP

The Common Public Radio Interface (CPRI) v6.0 (IP-CPRI-v6) Intel® FPGA intellectual property (IP) implements the CPRI Specification V6.0 (2013-08-30). CPRI is a high-speed serial interface for network radio equipment controllers (REC) to receive data from and provide data to remote radio equipment (RE). The CPRI v6.0 Intel FPGA IP core targets high-performance, remote, radio network applications. You can configure the CPRI v6.0 Intel FPGA IP core as an RE or an REC.

Please contact your local sales representative for more information.

The CPRI v6.0 Intel® FPGA IP core offers the following features:

  • Compliant with the CPRI Specification V6.0 (2013-08-30) Interface Specification available on the CPRI Industry Initiative website (www.cpri.info)
  • Supports REC and RE module configurations
  • Supports the following CPRI link features:
    • Configurable CPRI communication line bit rate (to 0.6144, 1.2288, 2.4576, 3.0720, 4.9152, 6.144, 8.11008, 9.8304, or 10.1376 Gbps) using Intel FPGA on-chip high-speed transceivers
    • CPRI line bit rate auto-rate negotiation support
    • Configurable and runtime programmable synchronization mode: master port or slave port on a CPRI link
    • Scrambling and descrambling at 8.11008 and 10.1376 Gbps
    • Optional scrambling and descrambling at 4.9152, 6.1440, and 9.8304 Gbps
    • Transmitter (TX) and receiver (RX) delay measurement and calibration
    • Optional support for single-trip delay calibration
    • Optional round-trip delay calibration
    • L1 link status and alarm (Z.130.0) control and status monitoring
    • Access to all vendor-specific data
    • Diagnostic parallel reverse loopback paths
    • Diagnostic serial and parallel forward loopback paths
    • Diagnostic stand-alone slave testing mode

Includes the following interfaces:

  • Register access interface to external or on-chip processor, using the Avalon® Memory-Mapped (Avalon-MM) interconnect specification.
  • Optional auxiliary (AUX) interface for full access to raw CPRI frame. Provides direct access to full radioframe, synchronizes the frame position with timing references, and enables routing application support from slave to master ports to implement daisy-chain topologies.
  • Optional choice of IEEE 802.3 100BASE-X compliant 10/100 Mbps MII or 1000BASE-X compliant 1Gbps GMII for Ethernet frame access.
  • Optional direct I/Q access interface enables integration of all user-defined air standard I/Q mapping schemes.
    • Optional external I/Q mapper and demapper modules with reference design support.
    • Optional external I/Q compression and decompression modules with reference design support.
  • Optional vendor-specific data access interfaces provide direct access to Vendor Specific (VS), Control AxC (Ctrl_AxC), and Real-time Vendor Specific (RTVS) subchannels.
  • Optional HDLC serial interface provides direct access to slow control and management subchannels.
  • Optional L1 inband interface provides direct access to Z.130.0 link status and alarm control word

 

CPRI v6.0 Intel® FPGA IP Core Performance: Device and Transceiver Speed Grade Support

Lower device speed grade numbers correspond to faster devices. The entry -x indicates that both the industrial speed grade Ix and the commercial speed grade Cx are supported for this device family and CPRI line bit rate. Table entries show slowest supported device speed grade or supported transceiver speed grade.

Device Family CPRI Line Bit Rate (Gbps)
0.6144 1.2288 2.4576 3.072 4.9152 6.1440 8.11008 9.8304 10.1376
Intel® Stratix® 10 FPGA 1 -2 / -3
Intel® Arria® 10 FPGA 1 -3 / -4
Intel® Stratix® V GT -3 / H3 -2 / H2
Intel® Stratix® V GX -4 / H3 -2 / H2
Intel® Arria® V GZ -4 / H3 -3 / H2 1
Intel® Arria® V GX -6 / H6 -5 / H4 -5 / H4 1
Intel® Arria® V GT -5/H3 1
Intel® Cyclone® V GT -7 / H5 1
Intel® Cyclone® V GX -8 / H7 -7 / H6 1

1 The CPRI v6.0 Intel FPGA IP core does not support this CPRI line bit rate for this device family.