Fast JPEG Encoder (BA116)

from Barco Silex

Block Diagram

Figure 1 shows a block diagram of the MegaCore® function.



The JPEG intellectual property (IP) core is intended for high-speed encoding of grayscale, color, or multi-scan images using ISO/IEC 10918-1 baseline coding standard. The encoder supports all features of the baseline standard, including restart markers, DNL, user-definable comments and application markers.

The BA116 is able to encode abbreviated-format or full-format images. If preferred, pre-defined default entropy and quantization tables are available. Its autonomous behavior, simple FIFO-like interfaces, and 100% synchronous structure, allow easy integration of the IP into complex systems with little effort. The ease of integration of this powerful IP core is reinforced by the stand-alone ability of the encoder that can be used in systems with very little CPU intervention.

  • Compliant with baseline JPEG (ISO/IEC 10918-1)
  • Support for color images (single and multi-scan format)
  • Single clock cycle per pixel component encoding
  • Single clock cycle Huffman encoding
  • Full header building capability
  • Automatic internal Huffman and quantization tables programming based on header data
  • Support for full-format and abbreviated-format, including restart markers and restart interval
  • One-pass encoding scheme with bit rate regulation if enabled
  • Simple FIFO interfaces for compress data and pixel data interfaces
  • Simple CPU interface for encoder and header programming
  • Easy-to-use status and control interface
  • Programmable external interrupt for event follow-up
  • Four entropy tables (two DC, two AC) and four quantization tables
  • Burst image-sequence encoding support for images with identical tables
  • 8x8 block-format pixel input with classical scan order
  • Fully scalable compressed-data and pixel interfaces
  • Fully synchronous hardware design
  • Throughputs ranging from sub common intermediate format (CIF) 25 MHz to SDTV to HDTV
  • Design encrypted files
  • VHDL testbenches
  • VHDL instantiation templates
  • Altera® Quartus® Prime implementation example
  • User guide

Table 1 lists the typical device utilization results for the MegaCore function.

Table 1. Typical Device Utilization for the MegaCore Function

Target Device Speed Grade Utilization Performance
Logic M9Ks DSP18
EP3C40C-66,782 logic elements (LEs)122105 MHz
EP2AGX95C-43,371 adaptive logic modules (ALMs)122175 MHz
For additional information, contact Barco Silex at:

Barco Silex
Scientific Park
Rue du Bosquet 7
B-1348 Louvain-la-Neuve
Tel: +32 10 486 403
Fax: +32 10 454 636