Reed-Solomon Compiler IP Core

Notice: The Reed-Solomon IP Core is now under obsolescence. For more details, refer to the product discontinuance notice, PDN1410.

The Reed-Solomon (RS) compiler offers a fully parameterizable RS coder and RS decoder. RS coder/decoders (CODECs) are widely used for error detection and correction in a wide range of digital signal processing (DSP) applications for storage, retrieval, and transmission of data.

The RS compiler has the following options:

  • Erasures-supporting option—the RS decoder can correct symbol errors up to the number of check symbols, if you give the location of the errors to the decoder
  • Variable encoding or decoding—you can vary the total number of symbols per codeword and the number of check symbols, in real time, from their minimum allowable values up to their selected values, when you are encoding or decoding
  • Error symbol output—the RS decoder finds the error values and location and adds these values in the Galois field to the input value
  • Bit-error output—either split count or full count

The RS Compiler generates a fully parameterizable RS function, allowing you to set the following parameters:

  • Number of bits per symbol
  • Number of symbols per codeword
  • Number of check symbols per codeword
  • Field polynomial
  • First root of generator polynomial
  • Space between roots in generator polynomial

The RS function offers the following other features:

  • Decoder features:
    • Variable option
    • Erasures-supportingoption
  • Encoder features variable architectures
  • Support for shortened codewords
  • Conforms to Consultative Committee for Space Data Systems (CCSDS) Recommendations for Telemetry Channel Coding, May 1999
  • Intellectual property (IP) functional simulation models for use in Intel® FPGA-supported VHDL and Verilog HDL simulators
  • Easy-to-use IP Toolbench interface:
    • Generates parameterized encoder or decoder
    • Generates customized testbench and customized Tcl script
  • DSP Builder for Intel FPGAs ready

 

Typical expected performance and utilization figures for this IP core are provided in the Reed-Solomon Compiler User Guide (PDF).

For technical support on this IP core, please visit Intel Premier Support. You may also search for related topics on this function in the Knowledge Center.