High-Speed AES Encryption Cores (RJDCEO/RJDCDO/RJDCED)

from D'Crypt Pte. Ltd.

Block Diagram

Figure 1 shows a block diagram of the AES encryption core.



  • >2.5 Gbits per second (Gbps) throughput for fiber-speed encryption
  • Key-agility on both encryption and decryption allows keys to be switched without stalling the core
  • Simple streaming architecture obviates the need for elaborate control logic outside the core
  • Bypass control allows data flow-through for selective encryption
  • Simple 32-bit data and key ports reduce logic required to interface to high-speed standards

Table 1 lists the typical device utilization results for the high-speed AES encryption and decryption megafunctions.

Table 1. Typical Device Utilization

Device Speed Grade Utilization Performance
Parameter Setting
Logic Cells EABs/ESBs (1)
APEX EP20K400E -1 6167 50 120.39 MHz Encryption Core
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APEX EP20K400E -1 6784 50 118.47 MHz Encryption Core
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  1. EAB = embedded array block; ESB = embedded system block < /li >

For additional information, contact D'Crypt at:

D'Crypt Pte Ltd.
20 Ayer Rajah Crescent
#08- 08 Technopreneur Centre
Singapore 139964
Phone: +65 773 9016
Fax: +65 873 0796
E-mail: ipcore@d-crypt.com
WWW: http://www.d-crypt.com