For larger ASIC designs that don't fit into a single FPGA, using multiple FPGAs for prototyping becomes a matter of partitioning a design across FPGAs and ensuring that design interconnects (e.g. bus signals) are maintained. Using the biggest FPGA available reduces the number of FPGAs required to implement a prototype, reducing the number of interconnects required between devices. For any interconnect scheme, Stratix series FPGAs offer the highest performance with signal integrity I/O pins, whether using LVDS or SSTL. This allows the FPGA prototype to perform as close to the initial design goals of the ASIC as possible.
Our largest Stratix series FPGAs are fully supported by major ASIC EDA vendors for software solutions, as well as third-party board vendors for off-the-shelf multi-FPGA solutions. The Quartus® Prime development software integrates into design flows that are close to, if not identical to, a typical ASIC flow, reducing the amount of learning required when using a new software tool. In addition, the tools can be invoked using scripting to match commonly used ASIC design methodologies.
All of our intellectual property (IP) cores that support Stratix series FPGAs can be licensed for use in an ASIC. The advantage of using our IP cores is that the IP is optimized to the Stratix family architecture, allowing it to run at ASIC-like speeds.
ASIC Prototyping EDA Partners
To aid and support the development of high-density designs, we have developed an ecosystem of EDA software partners and development board partners that help facilitate the complete design process.
ASIC Prototyping Third-Party Board Partners
Our third-party board partners provide off-the-shelf ASIC prototyping and verification solutions utilizing our FPGAs.